void TIMER1_IRQHandler(void)
{
if ((US_TICKER_TIMER->EVENTS_COMPARE[1] != 0) &&
((US_TICKER_TIMER->INTENSET & TIMER_INTENSET_COMPARE1_Msk) != 0)) {
US_TICKER_TIMER->EVENTS_COMPARE[1] = 0;
overflow++;
US_TICKER_TIMER->CC[1] = 0xFFFF;
if (timeStamp>0) {
timeStamp--;
if (timeStamp==0) {
us_ticker_clear_interrupt();
us_ticker_disable_interrupt();
us_ticker_irq_handler();
return;
}
}
}
if ((US_TICKER_TIMER->EVENTS_COMPARE[0] != 0) &&
((US_TICKER_TIMER->INTENSET & TIMER_INTENSET_COMPARE0_Msk) != 0)) {
us_ticker_clear_interrupt();
us_ticker_disable_interrupt();
if (timeStamp==0) {
us_ticker_irq_handler();
}
}
}
void us_ticker_free(void)
{
US_TICKER_COUNTER->TimerControl &= ~CMSDK_DUALTIMER1_CTRL_EN_Msk; // disable TIMER1
US_TICKER_INTERRUPT->TimerControl &= ~CMSDK_DUALTIMER2_CTRL_EN_Msk; // disable TIMER2
us_ticker_disable_interrupt();
us_ticker_inited = 0;
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
US_TICKER_COUNTER->TimerControl = 0x0ul; // disable TIMER1 and reset all control
US_TICKER_INTERRUPT->TimerControl = 0x0ul; // disable TIMER2 and reset all control
US_TICKER_COUNTER->TimerLoad = 0xFFFFFFFFul;
US_TICKER_INTERRUPT->TimerLoad = 0xFFFFFFFFul;
US_TICKER_COUNTER->TimerControl |= CMSDK_DUALTIMER1_CTRL_SIZE_Msk; // set TIMER1 to 32 bit counter
US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_SIZE_Msk; // set TIMER2 to 32 bit counter
US_TICKER_COUNTER->TimerControl |= 0x1 << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos; // set TIMER1 with 4 stages prescale
US_TICKER_INTERRUPT->TimerControl |= 0x1 << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos; // set TIMER2 with 4 stages prescale
US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_MODE_Msk; // set TIMER2 periodic mode
US_TICKER_INTERRUPT->TimerControl |= CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk; // set TIMER2 one-shot mode
US_TICKER_COUNTER->TimerControl |= CMSDK_DUALTIMER1_CTRL_EN_Msk; // enable TIMER1 counter
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
us_ticker_inited = 1;
}
void irq_handler(void) {
us_ticker_clear_interrupt();
/* Go through all the pending TimerEvents */
while (1) {
if (head == NULL) {
// There are no more TimerEvents left, so disable matches.
us_ticker_disable_interrupt();
return;
}
if ((int)(head->timestamp - us_ticker_read()) <= 0) {
// This event was in the past:
// point to the following one and execute its handler
ticker_event_t *p = head;
head = head->next;
event_handler(p->id); // NOTE: the handler can set new events
} else {
// This event and the following ones in the list are in the future:
// set it as next interrupt and return
us_ticker_set_interrupt(head->timestamp);
return;
}
}
}
void us_ticker_remove_event(ticker_event_t *obj) {
__disable_irq();
//if (obj) {
// remove this object from the list
if (head == obj) {
// first in the list, so just drop me
head = obj->next;
if (head == NULL) {
us_ticker_disable_interrupt();
} else {
us_ticker_set_interrupt(head->timestamp);
}
} else {
// find the object before me, then drop me
ticker_event_t* p = head;
while (p != NULL) {
if (p->next == obj) {
p->next = obj->next;
break;
}
p = p->next;
}
}
//}
__enable_irq();
}
void us_ticker_irq_handler(void) {
us_ticker_clear_interrupt();
/* Go through all the pending TimerEvents */
while (1) {
if (head == NULL) {
// There are no more TimerEvents left, so disable matches.
us_ticker_disable_interrupt();
return;
}
if ((int)(head->timestamp - us_ticker_read()) <= 0) {
// This event was in the past:
// point to the following one and execute its handler
ticker_event_t *p = head;
head = head->next;
if (event_handler != NULL) {
event_handler(p->id); // NOTE: the handler can set new events
}
/* Note: We continue back to examining the head because calling the
* event handler may have altered the chain of pending events. */
} else {
// This event and the following ones in the list are in the future:
// set it as next interrupt and return
us_ticker_set_interrupt(head->timestamp);
return;
}
}
}
void us_ticker_free(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
NVIC_DisableIRQ(US_TICKER_TIMER_IRQ);
TIMER_Enable(US_TICKER_TIMER, false);
CMU_ClockEnable(US_TICKER_TIMER_CLOCK, false);
us_ticker_inited = false;
}
}
void us_ticker_init(void)
{
if (ticker_inited) {
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
return;
}
ticker_inited = 1;
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(TIMER_MODINIT.rsetidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default.
timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
timer_base->CMP = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
}
void us_ticker_init(void)
{
if (ticker_inited) {
/* By HAL spec, ticker_init allows the ticker to keep counting and disables the
* ticker interrupt. */
us_ticker_disable_interrupt();
return;
}
ticker_inited = 1;
// Reset IP
SYS_ResetModule(TIMER_MODINIT.rsetidx);
// Select IP clock source
CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
// Enable IP clock
CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
// Timer for normal counter
uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
uint32_t cmp_timer = TMR_CMP_MAX;
MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
timer_base->CTL = TIMER_CONTINUOUS_MODE;
timer_base->PRECNT = prescale_timer;
timer_base->CMPR = cmp_timer;
NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
NVIC_DisableIRQ(TIMER_MODINIT.irq_n);
TIMER_EnableInt(timer_base);
TIMER_Start(timer_base);
/* Wait for timer to start counting and raise active flag */
while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
/* calling init again should cancel current interrupt */
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = true;
/* Enable clock for TIMERs */
CMU_ClockEnable(US_TICKER_TIMER_CLOCK, true);
if (REFERENCE_FREQUENCY > 24000000) {
US_TICKER_TIMER->CTRL = (US_TICKER_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) | (4 << _TIMER_CTRL_PRESC_SHIFT);
} else {
US_TICKER_TIMER->CTRL = (US_TICKER_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) | (3 << _TIMER_CTRL_PRESC_SHIFT);
}
/* Clear TIMER counter value */
TIMER_CounterSet(US_TICKER_TIMER, 0);
/* Start TIMER */
TIMER_Enable(US_TICKER_TIMER, true);
/* Select Compare Channel parameters */
TIMER_InitCC_TypeDef timerCCInit = TIMER_INITCC_DEFAULT;
timerCCInit.mode = timerCCModeCompare;
/* Configure Compare Channel 0 */
TIMER_InitCC(US_TICKER_TIMER, 0, &timerCCInit);
/* Enable interrupt vector in NVIC */
TIMER_IntClear(US_TICKER_TIMER, TIMER_IEN_CC0);
NVIC_SetVector(US_TICKER_TIMER_IRQ, (uint32_t) us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQ);
}
