// for the STM32F0, interrupts for DMA_CH4 and DMA_CH5 are combined void dma1_channel4_5_isr(void) { usart_disable_tx_dma(USART2); usart_disable_rx_dma(USART2); dma_clear_interrupt_flags(DMA1, DMA_CHANNEL4, DMA_TCIF); dma_clear_interrupt_flags(DMA1, DMA_CHANNEL5, DMA_TCIF); dma_disable_channel(DMA1, DMA_CHANNEL4); dma_disable_channel(DMA1, DMA_CHANNEL5); }
// DMA1_CHANNEL2 UART3_TX void dma1_channel2_isr(void) { if ((DMA1_ISR & DMA_ISR_TCIF2) != 0) { DMA1_IFCR |= DMA_IFCR_CTCIF2; dma_disable_transfer_complete_interrupt(DMA1, DMA_CHANNEL2); usart_disable_tx_dma(USART3); dma_disable_channel(DMA1, DMA_CHANNEL2); (*tx_done_handler)(); } }
void _USART_DMA_ISR(void) { DMA_IFCR(_USART_DMA) |= DMA_IFCR_CTCIF(_USART_DMA_CHANNEL); dma_disable_transfer_complete_interrupt(_USART_DMA, _USART_DMA_CHANNEL); usart_disable_tx_dma(_USART); dma_disable_channel(_USART_DMA, _USART_DMA_CHANNEL); busy = 0; }
/** Disable USART TX DMA. * \param s The USART DMA state structure. */ void usart_tx_dma_disable(usart_tx_dma_state* s) { /* Disable DMA stream interrupts with the NVIC. */ if (s->dma == DMA1) nvicDisableVector(dma_irq_lookup[0][s->stream]); else if (s->dma == DMA2) nvicDisableVector(dma_irq_lookup[1][s->stream]); /* Disable DMA stream. */ DMA_SCR(s->dma, s->stream) &= ~DMA_SxCR_EN; while (DMA_SCR(s->dma, s->stream) & DMA_SxCR_EN) ; /* Disable RX DMA on the USART. */ usart_disable_tx_dma(s->usart); }