/** * \brief Test physical loop-back with some characters in sunc mode. * * This function sends a character over USART on loop back to verify that init * and sending/receiving works. A jumper is connected on the USART. * * \param test Current test case. */ static void run_loopback_syncmode_test(const struct test_case *test) { uint8_t out_c = 'c'; uint8_t in_c = 0; port_pin_t sck_pin; sysclk_enable_module(POWER_RED_REG0, PRUSART0_bm); usart_set_mode(&CONF_UNIT_USART, USART_CMODE_SYNCHRONOUS_gc); sck_pin = IOPORT_CREATE_PIN(PORTE, 2); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH ); usart_spi_set_baudrate(&CONF_UNIT_USART, CONF_UNIT_BAUDRATE, sysclk_get_source_clock_hz()); usart_tx_enable(&CONF_UNIT_USART); usart_rx_enable(&CONF_UNIT_USART); usart_putchar(&CONF_UNIT_USART, out_c); in_c = usart_getchar(&CONF_UNIT_USART); test_assert_true(test, in_c == out_c, "Read character through sync mode is not correct: %d != %d", in_c, out_c); }
/** * \internal * \brief Helper function to read a byte from an arbitrary interface * * This function is used to hide what interface is used by the component * driver, e.g. the component driver does not need to know if USART in SPI * mode is used or the native SPI module. * * \retval uint8_t Byte of data read from the display controller */ __always_inline static uint8_t ili9341_read_byte(void) { uint8_t data; #if defined(CONF_ILI9341_USART_SPI) # if XMEGA /* Workaround for clearing the RXCIF for XMEGA */ usart_rx_enable(CONF_ILI9341_USART_SPI); usart_put(CONF_ILI9341_USART_SPI, 0xFF); while (!usart_rx_is_complete(CONF_ILI9341_USART_SPI)) { /* Do nothing */ } data = usart_get(CONF_ILI9341_USART_SPI); /* Workaround for clearing the RXCIF for XMEGA */ usart_rx_disable(CONF_ILI9341_USART_SPI); # else usart_spi_read_single(CONF_ILI9341_USART_SPI, &data); # endif #elif defined(CONF_ILI9341_SPI) spi_write_single(CONF_ILI9341_SPI, 0xFF); ili9341_wait_for_send_done(); /* Wait for RX to complete */ while (!spi_is_rx_full(CONF_ILI9341_SPI)) { /* Do nothing */ } spi_read_single(CONF_ILI9341_SPI, &data); #endif return data; }
/** * \brief Initialize USART in SPI master mode. * * This function initializes the USART module in SPI master mode using the * usart_spi_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. */ void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt) { usart->UBRR = 0; usart_enable_module_clock(usart); usart_set_mode(usart, USART_CMODE_MSPI_gc); if (opt->spimode == 1 || opt->spimode == 3) { usart->UCSRnC |= USART_UCPHA_bm; } else { usart->UCSRnC &= ~USART_UCPHA_bm; } if (opt->spimode == 2 || opt->spimode == 3) { usart->UCSRnC |= USART_UCPOL_bm; } else { usart->UCSRnC &= ~USART_UCPOL_bm; } if (opt->data_order) { usart->UCSRnC |= USART_DORD_bm; } else { usart->UCSRnC &= ~USART_DORD_bm; } usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_source_clock_hz()); usart_tx_enable(usart); usart_rx_enable(usart); }
void USART_L_init(void) { usart_set_mode(&Wireless_L_USART,USART_CMODE_ASYNCHRONOUS_gc); usart_format_set(&Wireless_L_USART,USART_CHSIZE_8BIT_gc,USART_PMODE_DISABLED_gc,false); usart_set_rx_interrupt_level(&Wireless_L_USART,USART_INT_LVL_MED); //usart_set_tx_interrupt_level(&Wireless_L_USART,USART_INT_LVL_MED); usart_set_baudrate(&Wireless_L_USART,USART_BUADRATE,F_CPU); usart_tx_enable(&Wireless_L_USART); usart_rx_enable(&Wireless_L_USART); }
/** * \brief Initialize USART in RS232 mode. * * This function initializes the USART module in RS232 mode using the * usart_rs232_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. */ void usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt) { usart_enable_module_clock(usart); usart_set_mode(usart, USART_CMODE_ASYNCHRONOUS_gc); usart_format_set(usart, opt->charlength, opt->paritytype, opt->stopbits); usart_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz()); usart_tx_enable(usart); usart_rx_enable(usart); }
/** * \brief Initialize USART in RS232 mode. * * This function initializes the USART module in RS232 mode using the * usart_rs232_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. * * \retval true if the initialization was successfull * \retval false if the initialization failed (error in baud rate calculation) */ bool usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt) { bool result; sysclk_enable_peripheral_clock(usart); usart_set_mode(usart, USART_CMODE_ASYNCHRONOUS_gc); usart_format_set(usart, opt->charlength, opt->paritytype, opt->stopbits); result = usart_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz()); usart_tx_enable(usart); usart_rx_enable(usart); return result; }
/** * \brief Initialize USART in SPI master mode. * * This function initializes the USART module in SPI master mode using the * usart_spi_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. */ void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt) { usart->UBRR = 0; usart_enable_module_clock(usart); usart_set_mode(usart, USART_CMODE_MSPI_gc); port_pin_t sck_pin; #ifdef USARTA0 if ((uintptr_t)usart == (uintptr_t)&UCSR0A) { sck_pin = IOPORT_CREATE_PIN(PORTE, 2); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH ); } #endif #ifdef USARTA1 if ((uintptr_t)usart == (uintptr_t)&UCSR1A) { sck_pin = IOPORT_CREATE_PIN(PORTD, 5); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH ); } #endif if (opt->spimode == 1 || opt->spimode == 3) { usart->UCSRnC |= USART_UCPHA_bm; } else { usart->UCSRnC &= ~USART_UCPHA_bm; } if (opt->spimode == 2 || opt->spimode == 3) { usart->UCSRnC |= USART_UCPOL_bm; } else { usart->UCSRnC &= ~USART_UCPOL_bm; } if (opt->data_order) { usart->UCSRnC |= USART_DORD_bm; } else { usart->UCSRnC &= ~USART_DORD_bm; } usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_source_clock_hz()); usart_tx_enable(usart); usart_rx_enable(usart); }
uint8_t sim900_send_sms(char * const p_sms_buf,const uint8_t isBufPGM, char * const p_sms_recipient,const uint8_t isRecPGM) { DEBUG_PRINT_FUNCTION_NAME(VERBOSE,"SIM900_SEND_SMS"); usart_rx_enable(USART_GPRS); const char * szret = sim900_cmd_with_retstring(PSTR("AT+CMGF=1\r\n"),true); if(szret!=sz_OK) { debug_string_P(NORMAL,PSTR ("(sim900_send_sms) [ERROR] got an error from AT+CMGF=1\r\n(sim900_send_sms) [ERROR] Instead of OK got : ")); debug_string_P(NORMAL,(NULL==szret) ? PSTR("NULL"):szret); //szret points to a flash storage string debug_string_P(NORMAL,szCRLF); return -1; } LITTLE_DELAY; sim900_put_string(PSTR("AT+CMGS=\""),PGM_STRING); sim900_put_string(p_sms_recipient,isRecPGM); sim900_put_string(PSTR("\"\r\n"),PGM_STRING); if(!sim900_wait_string(PSTR(">"),PGM_STRING)) { debug_string_P(NORMAL,PSTR ("(sim900_send_sms) [ERROR] got an error from AT+CMGS\r\n")); return -1; } LITTLE_DELAY; sim900_put_string(p_sms_buf,isBufPGM); sim900_put_string(PSTR("\x1A"),PGM_STRING); debug_string_P(NORMAL,PSTR ("(sim900_send_sms) out\r\n")); return 0; }
/** * \brief Initialize USART in SPI master mode. * * This function initializes the USART module in SPI master mode using the * usart_spi_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. */ void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt) { ioport_pin_t sck_pin; bool invert_sck; sysclk_enable_peripheral_clock(usart); usart_rx_disable(usart); /* configure Clock polarity using INVEN bit of the correct SCK I/O port **/ invert_sck = (opt->spimode == 2) || (opt->spimode == 3); UNUSED(invert_sck); #ifdef USARTC0 if ((uint16_t)usart == (uint16_t)&USARTC0) { sck_pin = IOPORT_CREATE_PIN(PORTC, 1); } #endif #ifdef USARTC1 if ((uint16_t)usart == (uint16_t)&USARTC1) { sck_pin = IOPORT_CREATE_PIN(PORTC, 5); } #endif #ifdef USARTD0 if ((uint16_t)usart == (uint16_t)&USARTD0) { sck_pin = IOPORT_CREATE_PIN(PORTD, 1); } #endif #ifdef USARTD1 if ((uint16_t)usart == (uint16_t)&USARTD1) { sck_pin = IOPORT_CREATE_PIN(PORTD, 5); } #endif #ifdef USARTE0 if ((uint16_t)usart == (uint16_t)&USARTE0) { sck_pin = IOPORT_CREATE_PIN(PORTE, 1); } #endif #ifdef USARTE1 if ((uint16_t)usart == (uint16_t)&USARTE1) { sck_pin = IOPORT_CREATE_PIN(PORTE, 5); } #endif #ifdef USARTF0 if ((uint16_t)usart == (uint16_t)&USARTF0) { sck_pin = IOPORT_CREATE_PIN(PORTF, 1); } #endif #ifdef USARTF1 if ((uint16_t)usart == (uint16_t)&USARTF1) { sck_pin = IOPORT_CREATE_PIN(PORTF, 5); } #endif /* Configure the USART output pin */ ioport_set_pin_dir(sck_pin, IOPORT_DIR_OUTPUT); ioport_set_pin_mode(sck_pin, IOPORT_MODE_TOTEM | (invert_sck? IOPORT_MODE_INVERT_PIN : 0)); ioport_set_pin_level(sck_pin, IOPORT_PIN_LEVEL_HIGH); usart_set_mode(usart, USART_CMODE_MSPI_gc); if (opt->spimode == 1 || opt->spimode == 3) { usart->CTRLC |= USART_UCPHA_bm; } else { usart->CTRLC &= ~USART_UCPHA_bm; } if (opt->data_order) { (usart)->CTRLC |= USART_DORD_bm; } else { (usart)->CTRLC &= ~USART_DORD_bm; } usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz()); usart_tx_enable(usart); usart_rx_enable(usart); }
uint8_t sim900_init() { DEBUG_PRINT_FUNCTION_NAME(VERBOSE,"SIM900_INIT"); #ifdef SIM900_USART_POLLED debug_string_P(NORMAL,PSTR("(sim900_init) code compiled with polled usart\r\n")); #else usart_interruptdriver_initialize(&sim900_usart_data,USART_GPRS,USART_INT_LVL_LO); usart_set_rx_interrupt_level(USART_GPRS,USART_INT_LVL_LO); usart_set_tx_interrupt_level(USART_GPRS,USART_INT_LVL_OFF); debug_string_P(NORMAL,PSTR("(sim900_init) code compiled with interrupt usart\r\n")); #endif init_sim: usart_rx_enable(USART_GPRS); sim900_power_off(); const char * szRET = NULL; int t=2; while(t--) { sim900_power_toggle(); uint8_t i=3; while(i--) { statusled_blink(1); sim900_put_string(sz_AT,PGM_STRING); szRET = sim900_wait_retstring(); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) trying to set a serial line speed\r\n")); } else break; } if(szRET==sz_OK) break; debug_string_P(NORMAL,PSTR("(SIM900_init) Not being able to connect to SIM900. Try to power it on again\r\n")); } if (szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) failed to synchronize with GPRS UART. The process will end here\r\n")); return -1; } //disabling echo back from the modem LITTLE_DELAY; szRET = sim900_cmd_with_retstring(PSTR("ATE0\r\n"),PGM_STRING); //sim900_wait_retstring(); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) this sim900 doesn't support ATE0\r\n")); } else { debug_string_P(VERBOSE,PSTR("(SIM900_init) correctly issued ATE0\r\n")); } LITTLE_DELAY; szRET = sim900_cmd_with_retstring(PSTR("AT+CREG=0\r\n"),PGM_STRING); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) this sim900 doesn't support AT+CREG\r\n")); } else { debug_string_P(VERBOSE,PSTR("(SIM900_init) correctly issued AT+CREG=0\r\n")); } //get the IMEI code LITTLE_DELAY; szRET = sim900_cmd_with_retstring(PSTR("AT+GSN=?\r\n"),true); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) this sim900 doesn't support AT+GSN\r\n")); } uint8_t i=IMEI_CODE_LEN; LITTLE_DELAY; sim900_cmd_with_read_string(PSTR("AT+GSN\r\n"),PGM_STRING,g_szIMEI,&i); sim900_wait_retstring(); debug_string_P(NORMAL,PSTR("IMEI code is : ")); debug_string(NORMAL,g_szIMEI,RAM_STRING); debug_string_P(NORMAL,szCRLF); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) AT+GSN messed up\r\n")); } else { debug_string_P(NORMAL,PSTR("(SIM900_init) AT+GSN GOT OK\r\n")); } LITTLE_DELAY; sim900_put_string(PSTR("AT+CPIN=?\r\n"),PGM_STRING); szRET = sim900_wait_retstring(); if(szRET!=sz_OK) { debug_string_P(NORMAL,PSTR("(SIM900_init) SIM is not present\r\n")); return 1; } LITTLE_DELAY; sim900_put_string(PSTR("AT+CPIN?\r\n"),PGM_STRING); szRET = sim900_wait4dictionary(tbl_CPIN_rets,NUM_OF_CPIN_RETURNS); char szBuf[16]; if(szRET==szCPIN_SIM_PIN) { debug_string_P(NORMAL,PSTR("(SIM900_init) SIM present and is PIN locked\r\n")); cfg_get_sim_pin(szBuf,8); if((szBuf[0]==0xFF) || (szBuf[0]==0x00)) { debug_string_P(NORMAL,PSTR("(SIM900_init) PIN code is not present in memory SIM will remain locked\r\n")); return 3; } else { debug_string_P(NORMAL,PSTR("(SIM900_init) PIN code is present in memory trying to unlock\r\nPIN: ")); debug_string(NORMAL,szBuf,RAM_STRING); debug_string_P(NORMAL,szCRLF); LITTLE_DELAY; sim900_put_string(PSTR("AT+CPIN="),PGM_STRING); sim900_put_string(szBuf,RAM_STRING); sim900_put_string(szCRLF,PGM_STRING); const char * ret = sim900_wait_retstring(); if(ret!=sz_OK) { debug_string_P(NORMAL,PSTR("(sim900_init) WARNING PIN is WRONG\r\n")); return 3; } } } else if (szRET==szCPIN_SIM_PUK) { debug_string_P(NORMAL,PSTR("(SIM900_init) SIM present and is PUK locked\r\n")); debug_string_P(NORMAL,PSTR("(SIM900_init) no PUK code, SIM init will fail here\r\n")); return 4; } for(i=0;i<18;++i) { statusled_blink(1); LITTLE_DELAY; sim900_put_string(PSTR("AT+CREG?\r\n"),PGM_STRING); uint8_t l = 16; memset(szBuf,0,16); sim900_read_string(szBuf,&l); if(strncasecmp_P(szBuf,PSTR("+CREG: 1,1"),5)!=0) { debug_string_P(NORMAL,PSTR("(SIM900_init) device is not answering as it should restarting it\r\n")); goto init_sim; } if(szBuf[9]=='1') { debug_string_P(NORMAL,PSTR("(SIM900_init) device correctly registered in the network\r\n")); break; } debug_string_P(NORMAL,PSTR("(SIM900_init) device answered ")); debug_string(NORMAL,szBuf,RAM_STRING); debug_string_P(NORMAL,PSTR(" seems not registered in the network\r\n")); debug_string_P(NORMAL,PSTR("(SIM900_init) will check again in 5 second\r\n")); delay_ms(5000); } return 0; }
/** * \brief Test setting different parameters of the USART module * * This function calls the different set functions, and verifies that the * correct values are being set. * * \param test Current test case. */ static void run_set_functions_test(const struct test_case *test) { bool success; /* Set USART mode and verify that it has been correctly set. */ usart_set_mode(&CONF_UNIT_USART, USART_CMODE_MSPI_gc); success = (CONF_UNIT_USART.UCSRnC & USART_UMSEL01_gm) == USART_CMODE_MSPI_gc; test_assert_true(test, success, "Trying to set USART mode to master SPI failed."); /* Set USART sync mode and verify that it has been correctly set. */ usart_set_mode(&CONF_UNIT_USART, USART_CMODE_SYNCHRONOUS_gc); success = (CONF_UNIT_USART.UCSRnC & USART_UMSEL01_gm) == USART_CMODE_SYNCHRONOUS_gc; test_assert_true(test, success, "Trying to set USART mode to sync mode failed."); /* Test enabling and disabling USART double baud*/ usart_double_baud_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnA & USART_U2X_bm); test_assert_true(test, success, "Trying to enable USART double baud failed."); usart_double_baud_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnA & USART_U2X_bm); test_assert_true(test, success, "Trying to disable USART double baud failed."); /* Test enabling and disabling USART RX */ usart_rx_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnB & USART_RXEN_bm); test_assert_true(test, success, "Trying to enable USART RX failed."); usart_rx_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnB & USART_RXEN_bm); test_assert_true(test, success, "Trying to disable USART RX failed."); /* Test enabling and disabling USART TX */ usart_tx_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnB & USART_TXEN_bm); test_assert_true(test, success, "Trying to enable USART TX failed."); usart_tx_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnB & USART_TXEN_bm); test_assert_true(test, success, "Trying to disable USART TX failed."); /* Test enabling and disabling USART TX complete interrupt*/ usart_tx_complete_interrupt_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnB & USART_TXC_bm); test_assert_true(test, success, "Trying to enable USART TX Complete interrupt failed."); usart_tx_complete_interrupt_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnB & USART_TXC_bm); test_assert_true(test, success, "Trying to disable USART TX Complete interrupt failed."); /* Test enabling and disabling USART RX complete interrupt*/ usart_rx_complete_interrupt_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnB & USART_RXC_bm); test_assert_true(test, success, "Trying to enable USART RX Complete interrupt failed."); usart_rx_complete_interrupt_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnB & USART_RXC_bm); test_assert_true(test, success, "Trying to disable USART RX Complete interrupt failed."); /* Test enabling and disabling USART data register empty interrupt*/ usart_data_empty_interrupt_enable(&CONF_UNIT_USART); success = (CONF_UNIT_USART.UCSRnB & USART_DRIE_bm); test_assert_true(test, success, "Trying to enable USART data register empty interrupt failed."); usart_data_empty_interrupt_disable(&CONF_UNIT_USART); success = !(CONF_UNIT_USART.UCSRnB & USART_DRIE_bm); test_assert_true(test, success, "Trying to disable USART data register empty interrupt failed."); /* Try to set format. */ usart_format_set(&CONF_UNIT_USART, USART_CHSIZE_8BIT_gc, USART_PMODE_EVEN_gc, true); success = !(CONF_UNIT_USART.UCSRnA & USART_FE_bm); test_assert_true(test, success, "Trying to set the Frame Format failed."); }
/** * \brief Initialize USART in SPI master mode. * * This function initializes the USART module in SPI master mode using the * usart_spi_options_t configuration structure and CPU frequency. * * \param usart The USART module. * \param opt The RS232 configuration option. */ void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt) { usart_enable_module_clock(usart); usart_set_mode(usart, USART_CMODE_MSPI_gc); port_pin_t sck_pin; if (opt->spimode == 1 || opt->spimode == 3) { //! \todo Fix when UCPHA_bm is added to header file. usart->CTRLC |= 0x02; } else { //! \todo Fix when UCPHA_bm is added to header file. usart->CTRLC &= ~0x02; } // configure Clock polarity using INVEN bit of the correct SCK I/O port if (opt->spimode == 2 || opt->spimode == 3) { #ifdef USARTC0 if ((uint16_t)usart == (uint16_t)&USARTC0) { sck_pin = IOPORT_CREATE_PIN(PORTC, 1); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTC1 if ((uint16_t)usart == (uint16_t)&USARTC1) { sck_pin = IOPORT_CREATE_PIN(PORTC, 5); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTD0 if ((uint16_t)usart == (uint16_t)&USARTD0) { sck_pin = IOPORT_CREATE_PIN(PORTD, 1); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTD1 if ((uint16_t)usart == (uint16_t)&USARTD1) { sck_pin = IOPORT_CREATE_PIN(PORTD, 5); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTE0 if ((uint16_t)usart == (uint16_t)&USARTE0) { sck_pin = IOPORT_CREATE_PIN(PORTE, 1); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTE1 if ((uint16_t)usart == (uint16_t)&USARTE1) { sck_pin = IOPORT_CREATE_PIN(PORTE, 5); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTF0 if ((uint16_t)usart == (uint16_t)&USARTF0) { sck_pin = IOPORT_CREATE_PIN(PORTF, 1); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif #ifdef USARTF1 if ((uint16_t)usart == (uint16_t)&USARTF1) { sck_pin = IOPORT_CREATE_PIN(PORTF, 5); ioport_configure_port_pin(ioport_pin_to_port(sck_pin), ioport_pin_to_mask(sck_pin), IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED); } #endif } usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz()); usart_tx_enable(usart); usart_rx_enable(usart); }