static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 addr;
u32 reg;
addr = le16_to_cpu(ctrl->wValue);
if (addr > 127) {
dev_dbg(dwc->dev, "invalid device address %d\n", addr);
return -EINVAL;
}
if (state == USB_STATE_CONFIGURED) {
dev_dbg(dwc->dev, "trying to set address when configured\n");
return -EINVAL;
}
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
reg |= DWC3_DCFG_DEVADDR(addr);
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
if (addr)
usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
else
usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
return 0;
}
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
int ret;
u32 reg;
dwc->start_config_issued = false;
cfg = le16_to_cpu(ctrl->wValue);
switch (state) {
case USB_STATE_DEFAULT:
return -EINVAL;
break;
case USB_STATE_ADDRESS:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
usb_gadget_set_state(&dwc->gadget,
USB_STATE_CONFIGURED);
if (dwc->ssphy_clear_auto_suspend_on_disconnect) {
reg = dwc3_readl(dwc->regs,
DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0),
reg);
}
if (!dwc->usb3_u1u2_disable || enable_dwc3_u1u2) {
/*
* Enable transition to U1/U2 state when
* nothing is pending from application.
*/
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= (DWC3_DCTL_ACCEPTU1ENA |
DWC3_DCTL_ACCEPTU2ENA);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
}
dwc->resize_fifos = true;
dev_dbg(dwc->dev, "resize fifos flag SET\n");
}
break;
case USB_STATE_CONFIGURED:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
if (!cfg)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_ADDRESS);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
int ret;
u32 reg;
dwc->start_config_issued = false;
cfg = le16_to_cpu(ctrl->wValue);
switch (state) {
case USB_STATE_DEFAULT:
return -EINVAL;
break;
case USB_STATE_ADDRESS:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
/*
* only change state if set_config has already
* been processed. If gadget driver returns
* USB_GADGET_DELAYED_STATUS, we will wait
* to change the state on the next usb_ep_queue()
*/
if (ret == 0)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_CONFIGURED);
/*
* Enable transition to U1/U2 state when
* nothing is pending from application.
*/
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc->resize_fifos = true;
dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
}
break;
case USB_STATE_CONFIGURED:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
if (!cfg && !ret)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_ADDRESS);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
int ret;
#ifndef CONFIG_USB_ANDROID_SAMSUNG_COMPOSITE
u32 reg;
#endif
dwc->start_config_issued = false;
cfg = le16_to_cpu(ctrl->wValue);
switch (state) {
case USB_STATE_DEFAULT:
return -EINVAL;
break;
case USB_STATE_ADDRESS:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
usb_gadget_set_state(&dwc->gadget,
USB_STATE_CONFIGURED);
#ifndef CONFIG_USB_ANDROID_SAMSUNG_COMPOSITE
/*
* Enable transition to U1/U2 state when
* nothing is pending from application.
*/
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
#endif
dwc->resize_fifos = true;
dev_dbg(dwc->dev, "resize fifos flag SET\n");
}
break;
case USB_STATE_CONFIGURED:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
if (!cfg)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_ADDRESS);
break;
default:
ret = -EINVAL;
}
return ret;
}
static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
const struct dwc3_event_depevt *event)
{
switch (event->status) {
case DEPEVT_STATUS_CONTROL_DATA:
/*
* We already have a DATA transfer in the controller's cache,
* if we receive a XferNotReady(DATA) we will ignore it, unless
* it's for the wrong direction.
*
* In that case, we must issue END_TRANSFER command to the Data
* Phase we already have started and issue SetStall on the
* control endpoint.
*/
if (dwc->ep0_expect_in != event->endpoint_number) {
struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
dev_err(dwc->dev, "unexpected direction for Data Phase\n");
dwc3_ep0_end_control_data(dwc, dep);
dwc3_ep0_stall_and_restart(dwc);
return;
}
break;
case DEPEVT_STATUS_CONTROL_STATUS:
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
return;
dwc->ep0state = EP0_STATUS_PHASE;
if (dwc->delayed_status) {
struct dwc3_ep *dep = dwc->eps[0];
WARN_ON_ONCE(event->endpoint_number != 1);
/*
* We should handle the delay STATUS phase here if the
* request for handling delay STATUS has been queued
* into the list.
*/
if (!list_empty(&dep->pending_list)) {
dwc->delayed_status = false;
usb_gadget_set_state(&dwc->gadget,
USB_STATE_CONFIGURED);
dwc3_ep0_do_control_status(dwc, event);
}
return;
}
dwc3_ep0_do_control_status(dwc, event);
}
}
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
int ret;
#ifndef CONFIG_USB_ANDROID_SAMSUNG_COMPOSITE
u32 reg;
#endif
dwc->start_config_issued = false;
cfg = le16_to_cpu(ctrl->wValue);
switch (state) {
case USB_STATE_DEFAULT:
return -EINVAL;
break;
case USB_STATE_ADDRESS:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
/*
* only change state if set_config has already
* been processed. If gadget driver returns
* USB_GADGET_DELAYED_STATUS, we will wait
* to change the state on the next usb_ep_queue()
*/
if (ret == 0)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_CONFIGURED);
#ifndef CONFIG_USB_ANDROID_SAMSUNG_COMPOSITE
/*
* NEGATIVE RX DETECTION
* Some host controllers (e.g. Intel) perform far-end
* receiver termination _negative_ detection while link
* is in U2 state. Synopsys PIPE PHY considers this
* signalling as U2 LFPS exit, moves to Recovery state
* and waits for training sequence which never comes.
* This finally leads to reconnection. Starting from
* DWC3 core 2.30a, GCTL register has bit U2EXIT_LFPS,
* which improves interoperability with such HCs.
*/
if (dwc->revision >= DWC3_REVISION_230A) {
/*
* Enable transition to U1/U2 state when
* nothing is pending from application.
*/
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= (DWC3_DCTL_ACCEPTU1ENA |
DWC3_DCTL_ACCEPTU2ENA);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
}
#endif
dwc->resize_fifos = true;
dev_dbg(dwc->dev, "resize fifos flag SET\n");
}
break;
case USB_STATE_CONFIGURED:
ret = dwc3_ep0_delegate_req(dwc, ctrl);
if (!cfg && !ret)
usb_gadget_set_state(&dwc->gadget,
USB_STATE_ADDRESS);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
struct dwc3_request *req)
{
struct dwc3 *dwc = dep->dwc;
req->request.actual = 0;
req->request.status = -EINPROGRESS;
req->epnum = dep->number;
list_add_tail(&req->list, &dep->request_list);
/*
* Gadget driver might not be quick enough to queue a request
* before we get a Transfer Not Ready event on this endpoint.
*
* In that case, we will set DWC3_EP_PENDING_REQUEST. When that
* flag is set, it's telling us that as soon as Gadget queues the
* required request, we should kick the transfer here because the
* IRQ we were waiting for is long gone.
*/
if (dep->flags & DWC3_EP_PENDING_REQUEST) {
unsigned direction;
direction = !!(dep->flags & DWC3_EP0_DIR_IN);
if (dwc->ep0state != EP0_DATA_PHASE) {
dev_WARN(dwc->dev, "Unexpected pending request\n");
return 0;
}
__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
DWC3_EP0_DIR_IN);
return 0;
}
/*
* In case gadget driver asked us to delay the STATUS phase,
* handle it here.
*/
if (dwc->delayed_status) {
unsigned direction;
direction = !dwc->ep0_expect_in;
dwc->delayed_status = false;
usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
if (dwc->ep0state == EP0_STATUS_PHASE)
__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
else
dev_dbg(dwc->dev, "too early for delayed status\n");
return 0;
}
/*
* Unfortunately we have uncovered a limitation wrt the Data Phase.
*
* Section 9.4 says we can wait for the XferNotReady(DATA) event to
* come before issueing Start Transfer command, but if we do, we will
* miss situations where the host starts another SETUP phase instead of
* the DATA phase. Such cases happen at least on TD.7.6 of the Link
* Layer Compliance Suite.
*
* The problem surfaces due to the fact that in case of back-to-back
* SETUP packets there will be no XferNotReady(DATA) generated and we
* will be stuck waiting for XferNotReady(DATA) forever.
*
* By looking at tables 9-13 and 9-14 of the Databook, we can see that
* it tells us to start Data Phase right away. It also mentions that if
* we receive a SETUP phase instead of the DATA phase, core will issue
* XferComplete for the DATA phase, before actually initiating it in
* the wire, with the TRB's status set to "SETUP_PENDING". Such status
* can only be used to print some debugging logs, as the core expects
* us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
* just so it completes right away, without transferring anything and,
* only then, we can go back to the SETUP phase.
*
* Because of this scenario, SNPS decided to change the programming
* model of control transfers and support on-demand transfers only for
* the STATUS phase. To fix the issue we have now, we will always wait
* for gadget driver to queue the DATA phase's struct usb_request, then
* start it right away.
*
* If we're actually in a 2-stage transfer, we will wait for
* XferNotReady(STATUS).
*/
if (dwc->three_stage_setup) {
unsigned direction;
direction = dwc->ep0_expect_in;
dwc->ep0state = EP0_DATA_PHASE;
__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
dep->flags &= ~DWC3_EP0_DIR_IN;
}
return 0;
}