/* ------------------------------------------------------------------------*//**
* @FUNCTION opp54xx_init
* @BRIEF initialize internal data
* @DESCRIPTION initialize internal data (architecture dependent)
*//*------------------------------------------------------------------------ */
void opp54xx_init(void)
{
opp_t opp;
/* ES1.0 */
static const opp_t mpu_opp_low_es1 = {OPP_LOW, 950000, 400000};
static const opp_t mpu_opp_nom_es1 = {OPP_NOM, 1040000, 800000};
static const opp_t mpu_opp_high_es1 = {OPP_HIGH, 1220000, 1100000};
static const opp_t mm_opp_low_es1 = {OPP_LOW, 950000, 177333};
static const opp_t mm_opp_nom_es1 = {OPP_NOM, 1040000, 354667};
static const opp_t mm_opp_high_es1 = {OPP_HIGH, 1220000, 532000};
static const opp_t core_opp_low_es1 = {OPP_LOW, 950000, 133000};
static const opp_t core_opp_nom_es1 = {OPP_NOM, 1040000, 2660000};
/* ES2.0 */
static const opp_t mpu_opp_low = {OPP_LOW, 880000, 500000};
static const opp_t mpu_opp_nom = {OPP_NOM, 1060000, 1000000};
static const opp_t mpu_opp_high = {OPP_HIGH, 1250000, 1500000};
static const opp_t mpu_opp_sb = {OPP_SB, 1290000, 1700000};
static const opp_t mm_opp_low = {OPP_LOW, 880000, 195000};
static const opp_t mm_opp_nom = {OPP_NOM, 1030000, 389000};
static const opp_t mm_opp_high = {OPP_HIGH, 1120000, 532000};
static const opp_t core_opp_low = {OPP_LOW, 880000, 133000};
static const opp_t core_opp_nom = {OPP_NOM, 1040000, 2660000};
#ifdef OPP54XX_DEBUG
int i, count;
voltdm54xx_id vdd;
#endif
if (!opp54xx_init_done) {
genlist_init(&vdd54xx_wkup_opp_list);
opp.name = OPP_NOM;
opp.voltage = 1.0;
opp.rate = clk54xx_sysclk_rate_get();
genlist_addtail(&vdd54xx_wkup_opp_list,
(void *) &opp, sizeof(opp_t));
genlist_init(&vdd54xx_mpu_opp_list);
if (cpu_revision_get() == REV_ES1_0) {
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_nom_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_high_es1, sizeof(opp_t));
genlist_init(&vdd54xx_mm_opp_list);
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_nom_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_high_es1, sizeof(opp_t));
genlist_init(&vdd54xx_core_opp_list);
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_nom_es1, sizeof(opp_t));
} else {
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_high, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_sb, sizeof(opp_t));
genlist_init(&vdd54xx_mm_opp_list);
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_high, sizeof(opp_t));
genlist_init(&vdd54xx_core_opp_list);
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_nom, sizeof(opp_t));
}
opp54xx_init_done = 1;
#ifdef OPP54XX_DEBUG
printf("%s(): init done.\n", __func__);
printf("OPP List:\n");
for (vdd = VDD54XX_WKUP; vdd <= VDD54XX_CORE; vdd++) {
count = genlist_getcount(
(genlist *) opp54xx_list_table_es1[vdd]);
printf(" %s (%d): ", voltdm54xx_name_get(vdd), count);
for (i = 0; i < count; i++) {
genlist_get(
(genlist *) opp54xx_list_table_es1[vdd],
i, (void *) &opp);
printf("%s (%.1lfMHz, %.3lfV)",
opp.name, khz2mhz(opp.rate),
uv2v(opp.voltage));
if (i != count - 1)
printf(", ");
}
printf(".\n");
}
#endif
}
}
const char *opp_by_voltage_get(const char *voltdm, unsigned short quiet)
{
int volt;
opp_t opp;
const genlist *opp_list;
int i, opp_count;
const char *opp_name = NULL;
const char *opp_name2 = NULL;
CHECK_NULL_ARG(voltdm, NULL);
opp_init();
volt = voltdm_nominal_voltage_get(voltdm);
if (volt < 0) {
dprintf("%s(%s): could not get voltage!\n", __func__, voltdm);
return NULL;
}
dprintf("%s(%s): nominal voltage is %duV\n", __func__, voltdm, volt);
opp_list = opp_list_get(voltdm);
if (opp_list == NULL) {
dprintf("%s(%s): could not get OPP list!\n", __func__, voltdm);
return NULL;
}
opp_count = opp_count_get(voltdm);
if (opp_count <= 0) {
dprintf("%s(%s): could not get OPP count!\n", __func__, voltdm);
return NULL;
}
dprintf("%s(%s): found %d possible OPP\n", __func__, voltdm, opp_count);
for (i = 0; i < opp_count; i++) {
genlist_get((genlist *) opp_list, i, (opp_t *) &opp);
dprintf("%s(%s): POR nominal voltage for %s is %duV\n",
__func__, voltdm, opp.name, opp.voltage);
if (volt == opp.voltage) {
/*
* OPP DPLL_CASC and OPP[50-NOM] shares the same
* voltage.
* This is also the case for OPP_NITRO and OPP_NITRO_SB.
* Must double-check with frequencies.
*/
if ((strcmp(opp.name, OPP_DPLL_CASC) != 0) &&
(strcmp(opp.name, OPP_NITRO) != 0)) {
opp_name = opp.name;
dprintf("%s(%s): OPP found: %s\n", __func__,
voltdm, opp_name);
break;
}
dprintf(
"%s(%s): %s found, double-checking using rates (same voltage apply to more than 1 OPP.\n",
__func__, voltdm, opp.name);
opp_name2 = opp_by_rate_get(voltdm, 1);
if (strcmp(opp_name2, opp.name) == 0) {
opp_name = opp.name;
dprintf("%s(%s): OPP found: %s\n", __func__,
voltdm, opp_name);
break;
}
dprintf(
"%s(%s): this was not %s, but probably the next one.\n",
__func__, voltdm, opp.name);
}
}
if ((quiet == 0) && (opp_name == NULL))
fprintf(stdout,
"omapconf: warning: no matching %s OPP for %lfV nominal voltage. Please check voltage against Data Manual recommendations.\n",
voltdm, uv2v(volt));
return opp_name;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION opp_show
* @BRIEF show current operating voltages and key clock rates.
* @RETURNS 0 in case of success
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_INTERNAL
* @param[in,out] stream: output file stream (opened, != NULL)
* @DESCRIPTION show current operating voltages and key clock rates.
*//*------------------------------------------------------------------------ */
int opp_show(FILE *stream)
{
int volt, volt2;
const char *opp_s, *opp_s2;
int temp;
int rate_mpu, rate_mpu_por;
int rate_dsp, rate_iva, rate_gpu;
int rate_dsp_por, rate_iva_por, rate_gpu_por, rate_aess_por;
int rate_l3, rate_l3_por;
int rate_l4, rate_emif, rate_lpddr2, rate_aess, rate_iss,
rate_fdif, rate_dss, rate_bb2d, rate_hsi;
mod_module_mode mmode;
int rate_cal, rate_ipu, rate_c2c;
char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
unsigned int row = 0;
unsigned int retry_cnt = 0;
unsigned int found = 0;
const genlist *voltdm_list;
int i, vdd_count;
const char voltdm[VOLTDM_MAX_NAME_LENGTH];
char prev_gov[CPUFREQ_GOV_MAX_NAME_LENGTH],
prev_gov2[CPUFREQ_GOV_MAX_NAME_LENGTH];
const char *temp_sensor;
/* Switch to userspace governor temporarily,
* so that OPP cannot change during audit and does not false it.
*/
cpufreq_scaling_governor_set("userspace", prev_gov);
autoadjust_table_init(table);
row = 0;
strncpy(table[row][1], "Temperature", TABLE_MAX_ELT_LEN);
strncpy(table[row][2], "Voltage", TABLE_MAX_ELT_LEN);
strncpy(table[row][3], "Frequency", TABLE_MAX_ELT_LEN);
strncpy(table[row][4], "OPerating Point", TABLE_MAX_ELT_LEN);
row++;
/*
* In order to make sure all details (OPP, voltage, clock rates) are
* coherent (due to potential OPP change in between), must use a loop,
* checking that OPP and voltage did not change and that at least ONE
* clock rate is aligned to expected rate for the detected OPP.
*/
dprintf("%s():\n", __func__);
voltdm_list = voltdm_list_get();
if (voltdm_list == NULL)
return OMAPCONF_ERR_INTERNAL;
vdd_count = voltdm_count_get();
if (vdd_count < 0)
return OMAPCONF_ERR_INTERNAL;
dprintf("found %d voltage domains\n", vdd_count);
for (i = 1; i < vdd_count; i++) {
genlist_get((genlist *) voltdm_list, i, (char *) &voltdm);
snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%s / VDD_CORE%u",
voltdm, i);
dprintf(" %s:\n", voltdm);
/* Retrieve OPP and clock rates */
retry_cnt = 0;
found = 0;
do {
dprintf(" TRY #%u:\n", retry_cnt);
if (retry_cnt == 0)
/* Print warning on first try */
opp_s = opp_get(voltdm, 0);
else
opp_s = opp_get(voltdm, 1);
if (opp_s == NULL) {
dprintf(" OPP NOT detected!\n");
opp_s = OPP_UNKNOWN;
} else {
dprintf(" OPP detected: %s\n", opp_s);
}
volt = voltdm_voltage_get(voltdm);
dprintf(" Voltage: %duV\n", volt);
if (strcmp(voltdm, "VDD_MPU") == 0) {
rate_mpu = mod_clk_rate_get("MPU");
if (strcmp(opp_s, OPP_UNKNOWN) != 0)
rate_mpu_por = mod_por_clk_rate_get(
"MPU", opp_s);
else
rate_mpu_por = -1;
dprintf(
" MPU Rate: %dKHz, POR Rate: %dKHz\n",
rate_mpu, rate_mpu_por);
} else if ((strcmp(voltdm, "VDD_IVA") == 0) ||
(strcmp(voltdm, "VDD_MM") == 0)) {
rate_dsp_por = -1;
rate_iva_por = -1;
rate_aess_por = -1;
rate_gpu_por = -1;
rate_dsp = mod_clk_rate_get("DSP");
rate_iva = mod_clk_rate_get("IVA");
if (cpu_is_omap44xx())
rate_aess = mod_clk_rate_get("AESS");
else if (cpu_is_omap54xx())
rate_gpu = mod_clk_rate_get("GPU");
if (strcmp(opp_s, OPP_UNKNOWN) != 0) {
rate_dsp_por = mod_por_clk_rate_get(
"DSP", opp_s);
rate_iva_por = mod_por_clk_rate_get(
"IVA", opp_s);
if (cpu_is_omap44xx())
rate_aess_por =
mod_por_clk_rate_get(
"AESS", opp_s);
else if (cpu_is_omap54xx())
rate_gpu_por =
mod_por_clk_rate_get(
"GPU", opp_s);
}
dprintf(
" DSP Rate: %dMHz, POR Rate: %dMHz\n",
rate_dsp, rate_dsp_por);
dprintf(
" IVA Rate: %dMHz, POR Rate: %dMHz\n",
rate_iva, rate_iva_por);
if (cpu_is_omap44xx()) {
dprintf(
" AESS Rate: %dMHz, POR Rate: %dMHz\n",
rate_aess, rate_aess_por);
} else if (cpu_is_omap54xx()) {
dprintf(
" GPU Rate: %dMHz, POR Rate: %dMHz\n",
rate_gpu, rate_gpu_por);
}
} else if (strcmp(voltdm, "VDD_CORE") == 0) {
rate_l3 = mod_clk_rate_get("L3");
if (strcmp(opp_s, OPP_UNKNOWN) != 0)
rate_l3_por = mod_por_clk_rate_get(
"L3", opp_s);
else
rate_l3_por = -1;
dprintf(
" L3_1 Rate: %dMHz, POR Rate: %dMHz\n",
rate_l3, rate_l3_por);
rate_emif = mod_clk_rate_get("EMIF");
rate_lpddr2 = mod_clk_rate_get("MEM");
rate_l4 = mod_clk_rate_get("L4");
if (cpu_is_omap44xx())
rate_gpu = mod_clk_rate_get("GPU");
else if (cpu_is_omap54xx())
rate_aess = mod_clk_rate_get("AESS");
rate_iss = mod_clk_rate_get("ISS");
rate_fdif = mod_clk_rate_get("FDIF");
if (!cpu_is_omap44xx())
rate_cal = mod_clk_rate_get("CAL");
else
rate_cal = -1;
rate_ipu = mod_clk_rate_get("IPU");
rate_dss = mod_clk_rate_get("DSS");
rate_hsi = mod_clk_rate_get("HSI");
if (cpu_is_omap4470() || cpu_is_omap54xx())
rate_bb2d = mod_clk_rate_get("BB2D");
else
rate_bb2d = -1;
rate_c2c = mod_clk_rate_get("C2C");
}
if (strcmp(opp_s, OPP_UNKNOWN) == 0) {
dprintf(
" Could not detect OPP, aborting for this domain.\n");
break;
}
opp_s2 = opp_get(voltdm, 1);
if (opp_s2 == NULL) {
dprintf(" OPP NOT detected! (2)\n");
opp_s2 = OPP_UNKNOWN;
} else {
dprintf(" OPP detected: %s (2)\n", opp_s2);
}
volt2 = voltdm_voltage_get(voltdm);
dprintf(" Voltage (2): %dV\n", volt2);
if (strcmp(voltdm, "VDD_MPU") == 0) {
found = ((rate_mpu == rate_mpu_por) &&
(strcmp(opp_s, opp_s2) == 0) &&
(volt == volt2));
} else if (strcmp(voltdm, "VDD_IVA") == 0) {
found = ((strcmp(opp_s, opp_s2) == 0) &&
(volt == volt2) &&
(((unsigned int) rate_dsp == (unsigned int) rate_dsp_por) ||
((unsigned int) rate_iva == (unsigned int) rate_iva_por) ||
((unsigned int) rate_aess == (unsigned int) rate_aess_por)));
} else if (strcmp(voltdm, "VDD_MM") == 0) {
found = ((strcmp(opp_s, opp_s2) == 0) &&
(volt == volt2) &&
((rate_dsp == rate_dsp_por) ||
(rate_iva == rate_iva_por) ||
(rate_gpu == rate_gpu_por)));
} else if (strcmp(voltdm, "VDD_CORE") == 0) {
found = ((strcmp(opp_s, opp_s2) == 0) &&
(volt == volt2) &&
(rate_l3 == rate_l3_por));
}
dprintf(" found=%u\n", found);
retry_cnt++;
} while ((retry_cnt < OPP_MAX_RETRY) && (found == 0));
/* Print temperature */
temp_sensor = temp_sensor_voltdm2sensor(voltdm);
if (temp_sensor == NULL) {
snprintf(table[row][1], TABLE_MAX_ELT_LEN, "NA");
} else {
temp = temp_sensor_get(temp_sensor);
if (temp != TEMP_ABSOLUTE_ZERO)
snprintf(table[row][1], TABLE_MAX_ELT_LEN,
"%dC / %dF", temp,
celcius2fahrenheit(temp));
else
snprintf(table[row][1], TABLE_MAX_ELT_LEN,
"NA");
}
/* Print voltage */
if (volt < 0)
snprintf(table[row][2], TABLE_MAX_ELT_LEN, "NA");
else if (!cpu_is_omap44xx())
snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.3lf V",
uv2v(volt));
else
snprintf(table[row][2], TABLE_MAX_ELT_LEN, "%.6lf V",
uv2v(volt));
/* Print OPP */
if (retry_cnt < OPP_MAX_RETRY) {
strncpy(table[row][4], opp_s,
TABLE_MAX_ELT_LEN);
} else {
fprintf(stderr,
"omapconf: too many %s OPP changes, could not retrieve it!!!\n",
voltdm);
strncpy(table[row][4], "ERROR", TABLE_MAX_ELT_LEN);
}
row++;
/* Print clock rates */
if (strcmp(voltdm, "VDD_MPU") == 0) {
if (cpu_is_online(1) == 1)
strncpy(table[row][0], " MPU (CPU1 ON)",
TABLE_MAX_ELT_LEN);
else
strncpy(table[row][0], " MPU (CPU1 OFF)",
TABLE_MAX_ELT_LEN);
snprintf(table[row][3], TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_mpu / 1000);
row += 2;
} else if ((strcmp(voltdm, "VDD_IVA") == 0) ||
(strcmp(voltdm, "VDD_MM") == 0)) {
strncpy(table[row][0], " IVA", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("IVA");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_iva / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_iva / 1000);
row++;
if (cpu_is_omap44xx()) {
strncpy(table[row][0], " AESS",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("AESS");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_aess / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_aess / 1000);
row++;
} else if (cpu_is_omap54xx()) {
strncpy(table[row][0], " GPU",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("GPU");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_gpu / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_gpu / 1000);
row++;
}
strncpy(table[row][0], " DSP", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("DSP");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_dsp / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_dsp / 1000);
row += 2;
} else if (strcmp(voltdm, "VDD_CORE") == 0) {
strncpy(table[row][0], " L3", TABLE_MAX_ELT_LEN);
snprintf(table[row][3], TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_l3 / 1000);
row++;
strncpy(table[row][0], " DMM/EMIF", TABLE_MAX_ELT_LEN);
snprintf(table[row][3], TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_emif / 1000);
row++;
strncpy(table[row][0], " LP-DDR2",
TABLE_MAX_ELT_LEN);
snprintf(table[row][3], TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_lpddr2 / 1000);
row++;
strncpy(table[row][0], " L4", TABLE_MAX_ELT_LEN);
snprintf(table[row][3], TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_l4 / 1000);
row++;
if (cpu_is_omap44xx()) {
strncpy(table[row][0], " GPU",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("GPU");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_gpu / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_gpu / 1000);
row++;
} else if (cpu_is_omap54xx()) {
strncpy(table[row][0], " AESS",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("AESS");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_aess / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_aess / 1000);
row++;
}
strncpy(table[row][0], " FDIF", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("FDIF");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_fdif / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_fdif / 1000);
row++;
if (cpu_is_omap54xx()) {
strncpy(table[row][0], " CAL",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("CAL");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_cal / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz",
rate_cal / 1000);
row++;
}
strncpy(table[row][0], " IPU", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("IPU");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_ipu / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_ipu / 1000);
row++;
if (cpu_is_omap44xx()) {
strncpy(table[row][0], " Cortex-M3 Cores",
TABLE_MAX_ELT_LEN);
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_ipu / 2000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_ipu / 2000);
row++;
} else if (cpu_is_omap54xx()) {
strncpy(table[row][0], " Cortex-M4 Cores",
TABLE_MAX_ELT_LEN);
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_ipu / 2000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_ipu / 2000);
row++;
}
strncpy(table[row][0], " ISS", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("ISS");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_iss / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_iss / 1000);
row++;
strncpy(table[row][0], " DSS", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("DSS");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_dss / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_dss / 1000);
row++;
if (cpu_is_omap4470() || cpu_is_omap54xx()) {
strncpy(table[row][0], " BB2D",
TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("BB2D");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3],
TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)",
rate_bb2d / 1000);
else
snprintf(table[row][3],
TABLE_MAX_ELT_LEN, " %-4d MHz",
rate_bb2d / 1000);
row++;
}
strncpy(table[row][0], " HSI", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("HSI");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_hsi / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_hsi / 1000);
row++;
strncpy(table[row][0], " C2C", TABLE_MAX_ELT_LEN);
mmode = mod_mode_get("C2C");
if (mmode == MOD_DISABLED_MODE)
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
"(%-4d MHz) (1)", rate_c2c / 1000);
else
snprintf(table[row][3], TABLE_MAX_ELT_LEN,
" %-4d MHz", rate_c2c / 1000);
row++;
}
}
/* Display table */
autoadjust_table_fprint(stream, table, row, 5);
fprintf(stream, "Notes:\n");
fprintf(stream,
" (1) Module is disabled, rate may not be relevant.\n\n");
/* Restore CPUFreq governor */
cpufreq_scaling_governor_set(prev_gov, prev_gov2);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION opp_dra7xx_init
* @BRIEF initialize internal data
* @DESCRIPTION initialize internal data (architecture dependent)
*//*------------------------------------------------------------------------ */
void opp_dra7xx_init(void)
{
static const opp_t core_opp_nom = {OPP_NOM, 1030000, 266000};
static const opp_t mpu_opp_nom = {OPP_NOM, 1060000, 1000000};
static const opp_t mpu_opp_od = {OPP_OD, 1160000, 1176000};
static const opp_t mpu_opp_high = {OPP_HIGH, 1250000, 1500000};
/*
* opp_dra7xx_list is just a reference of how many opp that a
* voltage manager has, so only need to add either dsp or eve,
* to indicating there are opp_nom, and opp_od for VDD_DSPEVE.
*/
static const opp_t dsp_opp_nom = {OPP_NOM, 1060000, 600000};
static const opp_t dsp_opp_od = {OPP_OD, 1150000, 700000};
static const opp_t iva_opp_nom = {OPP_NOM, 1060000, 388300};
static const opp_t iva_opp_od = {OPP_OD, 1160000, 430000};
static const opp_t iva_opp_high = {OPP_HIGH, 1250000, 532000};
static const opp_t gpu_opp_nom = {OPP_NOM, 1060000, 425600};
static const opp_t gpu_opp_od = {OPP_OD, 1160000, 500000};
static const opp_t gpu_opp_high = {OPP_HIGH, 1250000, 532000};
static const opp_t rtc_opp_nom = {OPP_NOM, 1030000, 34000};
#ifdef OPP_DRA7XX_DEBUG
int i, count;
voltdm_dra7xx_id vdd;
#endif
if (!opp_dra7xx_init_done) {
genlist_init(&vdd_dra7xx_core_opp_list);
genlist_addtail(&vdd_dra7xx_core_opp_list,
(void *) &core_opp_nom, sizeof(opp_t));
genlist_init(&vdd_dra7xx_mpu_opp_list);
genlist_addtail(&vdd_dra7xx_mpu_opp_list,
(void *) &mpu_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_mpu_opp_list,
(void *) &mpu_opp_od, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_mpu_opp_list,
(void *) &mpu_opp_high, sizeof(opp_t));
genlist_init(&vdd_dra7xx_dspeve_opp_list);
genlist_addtail(&vdd_dra7xx_dspeve_opp_list,
(void *) &dsp_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_dspeve_opp_list,
(void *) &dsp_opp_od, sizeof(opp_t));
genlist_init(&vdd_dra7xx_iva_opp_list);
genlist_addtail(&vdd_dra7xx_iva_opp_list,
(void *) &iva_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_iva_opp_list,
(void *) &iva_opp_od, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_iva_opp_list,
(void *) &iva_opp_high, sizeof(opp_t));
genlist_init(&vdd_dra7xx_gpu_opp_list);
genlist_addtail(&vdd_dra7xx_gpu_opp_list,
(void *) &gpu_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_gpu_opp_list,
(void *) &gpu_opp_od, sizeof(opp_t));
genlist_addtail(&vdd_dra7xx_gpu_opp_list,
(void *) &gpu_opp_high, sizeof(opp_t));
genlist_init(&vdd_dra7xx_rtc_opp_list);
genlist_addtail(&vdd_dra7xx_rtc_opp_list,
(void *) &rtc_opp_nom, sizeof(opp_t));
opp_dra7xx_init_done = 1;
#ifdef OPP_DRA7XX_DEBUG
printf("%s(): init done.\n", __func__);
printf("OPP List:\n");
for (vdd = VDD_DRA7XX_WKUP; vdd < VDD_DRA7XX_ID_MAX; vdd++) {
count = genlist_getcount(
(genlist *) opp_dra7xx_list_table[vdd]);
printf(" %s (%d): ", voltdm_dra7xx_name_get(vdd), count);
for (i = 0; i < count; i++) {
genlist_get(
(genlist *) opp_dra7xx_list_table[vdd],
i, (void *) &opp);
printf("%s (%.1lfMHz, %.3lfV)",
opp.name, khz2mhz(opp.rate),
uv2v(opp.voltage));
if (i != count - 1)
printf(", ");
}
printf(".\n");
}
#endif
}
}
