static UINT32 opPUSHM(v60_state *cpustate)
{
int i;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 2;
// Read the bit register list
cpustate->amlength1 = ReadAM(cpustate);
if (cpustate->amout & (1 << 31))
{
cpustate->SP -= 4;
cpustate->program->write_dword_unaligned(cpustate->SP, v60ReadPSW(cpustate));
}
for (i = 0;i < 31;i++)
if (cpustate->amout & (1 << (30 - i)))
{
cpustate->SP -= 4;
cpustate->program->write_dword_unaligned(cpustate->SP, cpustate->reg[(30 - i)]);
}
return cpustate->amlength1 + 1;
}
UINT32 opPUSHM(void)
{
int i;
modAdd=PC+1;
modDim=2;
/* Read the bit register list */
amLength1=ReadAM();
if (amOut & (1<<31))
{
SP -= 4;
MemWrite32(SP,v60ReadPSW());
}
for (i=0;i<31;i++)
if (amOut & (1<<(30-i)))
{
SP -= 4;
MemWrite32(SP,v60.reg[(30-i)]);
}
return amLength1 + 1;
}
static UINT32 opPOPM(v60_state *cpustate)
{
int i;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 2;
// Read the bit register list
cpustate->amlength1 = ReadAM(cpustate);
for (i = 0;i < 31;i++)
if (cpustate->amout & (1 << i))
{
cpustate->reg[i] = cpustate->program->read_dword_unaligned(cpustate->SP);
cpustate->SP += 4;
}
if (cpustate->amout & (1 << 31))
{
v60WritePSW(cpustate, (v60ReadPSW(cpustate) & 0xffff0000) | cpustate->program->read_word_unaligned(cpustate->SP));
cpustate->SP += 4;
}
return cpustate->amlength1 + 1;
}
UINT32 opPOPM(void)
{
int i;
modAdd=PC+1;
modDim=2;
/* Read the bit register list */
amLength1=ReadAM();
for (i=0;i<31;i++)
if (amOut & (1<<i))
{
v60.reg[i] = MemRead32(SP);
SP += 4;
}
if (amOut & (1<<31))
{
v60WritePSW((v60ReadPSW() & 0xffff0000) | MemRead16(SP));
SP += 4;
}
return amLength1 + 1;
}
void v60_device::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
case V60_PSW:
m_debugger_temp = v60ReadPSW();
break;
}
}
static UINT32 opGETPSW(v60_state *cpustate)
{
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 2;
cpustate->modwritevalw = v60ReadPSW(cpustate);
// Write cpustate->PSW to the operand
cpustate->amlength1 = WriteAM(cpustate);
return cpustate->amlength1 + 1;
}
UINT32 opGETPSW(void)
{
modAdd=PC + 1;
modDim=2;
modWriteValW=v60ReadPSW();
/* Write PSW to the operand */
amLength1=WriteAM();
return amLength1 + 1;
}
static UINT32 opSTTASK(v60_state *cpustate)
{
int i;
UINT32 adr;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 2;
cpustate->amlength1 = ReadAM(cpustate);
adr = cpustate->TR;
v60WritePSW(cpustate, v60ReadPSW(cpustate) | 0x10000000);
v60SaveStack(cpustate);
cpustate->program->write_dword_unaligned(adr, cpustate->TKCW);
adr += 4;
if(cpustate->SYCW & 0x100) {
cpustate->program->write_dword_unaligned(adr, cpustate->L0SP);
adr += 4;
}
if(cpustate->SYCW & 0x200) {
cpustate->program->write_dword_unaligned(adr, cpustate->L1SP);
adr += 4;
}
if(cpustate->SYCW & 0x400) {
cpustate->program->write_dword_unaligned(adr, cpustate->L2SP);
adr += 4;
}
if(cpustate->SYCW & 0x800) {
cpustate->program->write_dword_unaligned(adr, cpustate->L3SP);
adr += 4;
}
// 31 registers supported, _not_ 32
for(i = 0; i < 31; i++)
if(cpustate->amout & (1 << i)) {
cpustate->program->write_dword_unaligned(adr, cpustate->reg[i]);
adr += 4;
}
// #### Ignore the virtual addressing crap.
return cpustate->amlength1 + 1;
}
UINT32 opSTTASK(void)
{
int i;
UINT32 adr;
modAdd=PC + 1;
modDim=2;
amLength1 = ReadAM();
adr = TR;
v60WritePSW(v60ReadPSW() | 0x10000000);
v60SaveStack();
MemWrite32(adr, TKCW);
adr += 4;
if(SYCW & 0x100) {
MemWrite32(adr, L0SP);
adr += 4;
}
if(SYCW & 0x200) {
MemWrite32(adr, L1SP);
adr += 4;
}
if(SYCW & 0x400) {
MemWrite32(adr, L2SP);
adr += 4;
}
if(SYCW & 0x800) {
MemWrite32(adr, L3SP);
adr += 4;
}
/* 31 registers supported, _not_ 32 */
for(i=0; i<31; i++)
if(amOut & (1<<i)) {
MemWrite32(adr, v60.reg[i]);
adr += 4;
}
/* #### Ignore the virtual addressing crap. */
return amLength1 + 1;
}
UINT32 v60_device::v60_update_psw_for_exception(int is_interrupt, int target_level)
{
UINT32 oldPSW = v60ReadPSW();
UINT32 newPSW = oldPSW;
// Change to interrupt context
newPSW &= ~(3 << 24); // PSW.EL = 0
newPSW |= target_level << 24; // set target level
newPSW &= ~(1 << 18); // PSW.IE = 0
newPSW &= ~(1 << 16); // PSW.TE = 0
newPSW &= ~(1 << 27); // PSW.TP = 0
newPSW &= ~(1 << 17); // PSW.AE = 0
newPSW &= ~(1 << 29); // PSW.EM = 0
if (is_interrupt)
newPSW |= (1 << 28);// PSW.IS = 1
newPSW |= (1 << 31); // PSW.ASA = 1
v60WritePSW(newPSW);
return oldPSW;
}
