int cleanup_before_linux(void) { unsigned int i; /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); /* turn off I/D-cache */ icache_disable(); dcache_disable(); /* invalidate I-cache */ cache_flush(); #ifndef CONFIG_L2_OFF /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif return 0; }
int cleanup_before_linux(void) { unsigned int i; #ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE extern void clear_mfgmode_mem(void); clear_mfgmode_mem(); #endif #ifdef CONFIG_VIDEO_MX5 ipu_disable_channel(MEM_BG_SYNC); ipu_uninit_channel(MEM_BG_SYNC); #endif /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); /* flush cache */ cache_flush(); /* turn off I/D-cache */ icache_disable(); /* invalidate D-cache */ dcache_disable(); #ifndef CONFIG_L2_OFF /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); /* turn off MMU */ MMU_OFF(); #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif return 0; }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. **********************************************************/ void s_init(void) { int i; int external_boot = 0; int in_sdram = running_in_sdram(); watchdog_init(); external_boot = (get_boot_type() == 0x1F) ? 1 : 0; /* Right now flushing at low MPU speed. Need to move after clock init */ v7_flush_dcache_all(get_device_type(), external_boot); try_unlock_memory(); if (cpu_is_3410()) { /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); } #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif set_muxconf_regs(); delay(100); /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ /* Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ setup_auxcr(get_device_type(), external_boot); prcm_init(); per_clocks_enable(); }
/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = is_running_in_sdram(); watchdog_init(); try_unlock_memory(); /* * Right now flushing at low MPU speed. * Need to move after clock init */ v7_flush_dcache_all(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); delay(100); prcm_init(); per_clocks_enable(); if (!in_sdram) sdrc_init(); }