int
smg_match(device_t parent, cfdata_t match, void *aux)
{
struct vsbus_attach_args * const va = aux;
volatile uint16_t *ccmd;
volatile uint16_t *cfgtst;
uint16_t tmp, tmp2;
if (vax_boardtype == VAX_BTYP_49 || vax_boardtype == VAX_BTYP_53)
return 0;
ccmd = (uint16_t *)va->va_addr;
cfgtst = (uint16_t *)vax_map_physmem(VS_CFGTST, 1);
/*
* Try to find the cursor chip by testing the flip-flop.
* If nonexistent, no glass tty.
*/
ccmd[0] = CUR_CMD_HSHI|CUR_CMD_FOPB;
DELAY(300000);
tmp = cfgtst[0];
ccmd[0] = CUR_CMD_TEST|CUR_CMD_HSHI;
DELAY(300000);
tmp2 = cfgtst[0];
vax_unmap_physmem((vaddr_t)cfgtst, 1);
if (tmp2 != tmp)
return 20; /* Using periodic interrupt */
else
return 0;
}
void
ubi_attach(device_t parent, device_t self, void *aux)
{
struct sbi_attach_args sa;
printf("\n");
sa.sa_base = (bus_addr_t)NEX730;
#define NEXPAGES (sizeof(struct nexus) / VAX_NBPG)
#if 0
/*
* Probe for memory, can be in the first 4 slots.
*/
for (sa.sa_nexnum = 0; sa.sa_nexnum < 4; sa.sa_nexnum++) {
sa.sa_ioh = vax_map_physmem(NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
if (badaddr((caddr_t)sa.sa_ioh, 4)) {
vax_unmap_physmem((vaddr_t)sa.sa_ioh, NEXPAGES);
} else {
sa.sa_type = NEX_MEM16;
config_found(self, (void*)&sa, ubi_print);
}
}
#endif
/* VAX 730 fixed configuration */
/* memory */
sa.sa_nexnum = 0;
sa.sa_ioh = vax_map_physmem((int)NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
sa.sa_type = NEX_MEM16;
config_found(self, (void*)&sa, ubi_print);
printf("\n");
/* generic UBA */
sa.sa_nexnum = 3;
sa.sa_ioh = vax_map_physmem((int)NEX730 +
sizeof(struct nexus) * sa.sa_nexnum, NEXPAGES);
sa.sa_type = NEX_UBA0;
config_found(self, (void*)&sa, ubi_print);
}
static void
nmi_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct nmi_attach_args na;
int nbia, *r = 0;
printf("\n");
/* One CPU is always found */
na.slot = 20;
config_found(self, (void *)&na, nmi_mainbus_print);
/* Check for a second one */
if (vax_boardtype == VAX_BTYP_8800) {
na.slot = 21;
config_found(self, (void *)&na, nmi_mainbus_print);
}
/* One memory adapter is also present */
na.slot = 10;
config_found(self, (void *)&na, nmi_mainbus_print);
/* Enable BI interrupts */
mtpr(NICTRL_DEV0|NICTRL_DEV1|NICTRL_MNF, PR_NICTRL);
/* Search for NBIA/NBIB adapters */
for (nbia = 0; nbia < 2; nbia++) {
if (r)
vax_unmap_physmem((vaddr_t)r, 1);
r = (int *)vax_map_physmem(NBIA_REGS(nbia), 1);
if (badaddr((caddr_t)r, 4))
continue;
na.slot = 2 * nbia;
if (r[1] & 2)
config_found(self, (void *)&na, nmi_mainbus_print);
na.slot++;
if (r[1] & 4)
config_found(self, (void *)&na, nmi_mainbus_print);
}
}
void
ka410_conf()
{
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
printf("cpu: KA410\n");
break;
case VAX_TYP_CVAX:
printf("cpu: KA41/42\n");
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
printf("cpu: Enabling primary cache, ");
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE,
PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
printf("secondary cache\n");
ka41_cache_enable();
} else
printf("no secondary cache present\n");
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
void
ze_mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args * const ma = aux;
struct ze_softc * const sc = device_private(self);
const struct sgec_data * const sd = ze_find();
const uint32_t *ea;
size_t i;
int error;
sc->sc_dev = self;
/*
* Map in SGEC registers.
*/
sc->sc_dmat = ma->ma_dmat;
sc->sc_iot = ma->ma_iot;
sc->sc_intvec = sd->sd_intvec;
error = bus_space_map(sc->sc_iot, sd->sd_addr, PAGE_SIZE, 0,
&sc->sc_ioh);
if (error) {
aprint_error(": failed to map %#lx: %d\n", sd->sd_addr, error);
return;
}
/*
* Map in, read and release ethernet rom address.
*/
ea = (uint32_t *)vax_map_physmem(sd->sd_rom, 1);
for (i = 0; i < ETHER_ADDR_LEN; i++)
sc->sc_enaddr[i] = (ea[i] >> sd->sd_romshift) & 0377;
vax_unmap_physmem((vaddr_t)ea, 1);
scb_vecalloc(sc->sc_intvec, (void (*)(void *)) sgec_intr, sc,
SCB_ISTACK, &sc->sc_intrcnt);
sgec_attach(sc);
}
void
ka410_conf(void)
{
struct cpu_info * const ci = curcpu();
struct vs_cpu *ka410_cpu;
ka410_cpu = (struct vs_cpu *)vax_map_physmem(VS_REGS, 1);
switch (vax_cputype) {
case VAX_TYP_UV2:
ka410_cpu->vc_410mser = 1;
ci->ci_cpustr = "KA410, UV2";
break;
case VAX_TYP_CVAX:
ka410_cpu->vc_vdcorg = 0; /* XXX */
ka410_cpu->vc_parctl = PARCTL_CPEN | PARCTL_DPEN ;
mtpr(KA420_CADR_S2E|KA420_CADR_S1E|KA420_CADR_ISE|KA420_CADR_DSE, PR_CADR);
if (vax_confdata & KA420_CFG_CACHPR) {
l2cache = (void *)vax_map_physmem(KA420_CH2_BASE,
(KA420_CH2_SIZE / VAX_NBPG));
cacr = (void *)vax_map_physmem(KA420_CACR, 1);
ka41_cache_enable();
ci->ci_cpustr =
"KA420, CVAX, 1KB L1 cache, 64KB L2 cache";
} else {
ci->ci_cpustr = "KA420, CVAX, 1KB L1 cache";
}
}
/* Done with ka410_cpu - release it */
vax_unmap_physmem((vaddr_t)ka410_cpu, 1);
/*
* Setup parameters necessary to read time from clock chip.
*/
clk_adrshift = 1; /* Addressed at long's... */
clk_tweak = 2; /* ...and shift two */
clk_page = (short *)vax_map_physmem(KA420_WAT_BASE, 1);
}
void
le_fwio_attach(struct device *parent, struct device *self, void *aux)
{
struct fwio_attach_args *faa = (struct fwio_attach_args *)aux;
struct le_fwio_softc *lsc = (struct le_fwio_softc *)self;
struct lance_softc *sc = &lsc->sc_am7990.lsc;
unsigned int vec;
uint32_t *esar;
int i;
vec = faa->faa_vecbase + FBIC_DEVIRQ1 * 4;
printf(" vec %d", vec);
/*
* Map registers.
*/
lsc->sc_rdp = (volatile uint16_t *)
vax_map_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
lsc->sc_rap = lsc->sc_rdp + 2;
/*
* Register access functions.
*/
sc->sc_rdcsr = le_fwio_rdcsr;
sc->sc_wrcsr = le_fwio_wrcsr;
/*
* Map buffers.
*/
sc->sc_mem = (void *)uvm_km_valloc(kernel_map, FWIO_LANCE_BUF_SIZE);
if (sc->sc_mem == NULL) {
vax_unmap_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
printf(": can't map buffers\n");
return;
}
ioaccess((vaddr_t)sc->sc_mem, faa->faa_base +
FWIO_LANCE_BUF_OFFSET, FWIO_LANCE_BUF_SIZE >> VAX_PGSHIFT);
sc->sc_addr = FWIO_LANCE_BUF_OFFSET;
sc->sc_memsize = FWIO_LANCE_BUF_SIZE;
sc->sc_conf3 = 0;
sc->sc_copytodesc = lance_copytobuf_contig;
sc->sc_copyfromdesc = lance_copyfrombuf_contig;
sc->sc_copytobuf = lance_copytobuf_contig;
sc->sc_copyfrombuf = lance_copyfrombuf_contig;
sc->sc_zerobuf = lance_zerobuf_contig;
/*
* Get the Ethernet address from the Station Address ROM.
*/
esar = (uint32_t *)vax_map_physmem(faa->faa_base + FWIO_ESAR_OFFSET, 1);
for (i = 0; i < 6; i++)
sc->sc_arpcom.ac_enaddr[i] =
(esar[i] & FWIO_ESAR_MASK) >> FWIO_ESAR_SHIFT;
vax_unmap_physmem((vaddr_t)esar, 1);
/*
* Register interrupt handler.
*/
if (mbus_intr_establish(vec, IPL_NET, le_fwio_intr, sc,
self->dv_xname) != 0) {
vax_unmap_physmem(faa->faa_base + FWIO_LANCE_REG_OFFSET, 1);
uvm_km_free(kernel_map, (vaddr_t)sc->sc_mem,
FWIO_LANCE_BUF_SIZE);
printf(": can't establish interrupt\n");
return;
}
/*
* Complete attachment.
*/
am7990_config(&lsc->sc_am7990);
}
void
legss_attach(struct device *parent, struct device *self, void *aux)
{
struct legss_softc *sc = (struct legss_softc *)self;
struct legss_screen *scr;
struct wsemuldisplaydev_attach_args aa;
int console;
vaddr_t tmp;
extern struct consdev wsdisplay_cons;
console = (vax_confdata & 0x60) != 0 && cn_tab == &wsdisplay_cons;
if (console) {
scr = &legss_consscr;
sc->sc_nscreens = 1;
} else {
scr = malloc(sizeof(struct legss_screen), M_DEVBUF, M_NOWAIT);
if (scr == NULL) {
printf(": can not allocate memory\n");
return;
}
tmp = vax_map_physmem(LEGSS_BASE + LEGSS_VRAM_OFFSET, 1);
if (tmp == 0L) {
printf(": can not probe depth\n");
goto bad1;
}
scr->ss_depth = legss_probe_depth(tmp);
vax_unmap_physmem(tmp, 1);
if (scr->ss_depth == 0) {
printf(": unrecognized depth\n");
goto bad1;
}
scr->ss_vram = vax_map_physmem(LEGSS_BASE + LEGSS_VRAM_OFFSET,
(LEGSS_VISHEIGHT * LEGSS_WIDTH * 32 / NBBY) / VAX_NBPG);
if (scr->ss_vram == 0L) {
printf(": can not map frame buffer\n");
goto bad1;
}
if (legss_setup_screen(scr) != 0) {
printf(": initialization failed\n");
goto bad2;
}
}
sc->sc_scr = scr;
printf(": %dx%d %d plane color framebuffer\n",
LEGSS_VISWIDTH, LEGSS_VISHEIGHT, scr->ss_depth);
aa.console = console;
aa.scrdata = &legss_screenlist;
aa.accessops = &legss_accessops;
aa.accesscookie = sc;
aa.defaultscreens = 0;
config_found(self, &aa, wsemuldisplaydevprint);
return;
bad2:
vax_unmap_physmem(scr->ss_vram,
(LEGSS_VISHEIGHT * LEGSS_WIDTH * 32 / NBBY) / VAX_NBPG);
bad1:
free(scr, M_DEVBUF);
}
