Esempio n. 1
0
static int vbi_open(struct saa7146_dev *dev, struct file *file)
{
    struct saa7146_fh *fh = file->private_data;

    u32 arbtr_ctrl	= saa7146_read(dev, PCI_BT_V1);
    int ret = 0;

    DEB_VBI(("dev:%p, fh:%p\n",dev,fh));

    ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
    if (0 == ret) {
        DEB_S(("cannot get vbi RESOURCE_DMA3_BRS resource\n"));
        return -EBUSY;
    }

    /* adjust arbitrition control for video dma 3 */
    arbtr_ctrl &= ~0x1f0000;
    arbtr_ctrl |=  0x1d0000;
    saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
    saa7146_write(dev, MC2, (MASK_04|MASK_20));

    memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt));

    fh->vbi_fmt.sampling_rate	= 27000000;
    fh->vbi_fmt.offset		= 248; /* todo */
    fh->vbi_fmt.samples_per_line	= vbi_pixel_to_capture;
    fh->vbi_fmt.sample_format	= V4L2_PIX_FMT_GREY;

    fh->vbi_fmt.start[0] = 5;
    fh->vbi_fmt.count[0] = 16;
    fh->vbi_fmt.start[1] = 312;
    fh->vbi_fmt.count[1] = 16;

    videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
                           &dev->pci->dev, &dev->slock,
                           V4L2_BUF_TYPE_VBI_CAPTURE,
                           V4L2_FIELD_SEQ_TB,
                           sizeof(struct saa7146_buf),
                           file);

    init_timer(&fh->vbi_read_timeout);
    fh->vbi_read_timeout.function = vbi_read_timeout;
    fh->vbi_read_timeout.data = (unsigned long)file;

    /* initialize the brs */
    if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
        saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
    } else {
        saa7146_write(dev, BRS_CTRL, 0x00000001);

        if (0 != (ret = vbi_workaround(dev))) {
            DEB_VBI(("vbi workaround failed!\n"));
            /* return ret;*/
        }
    }

    /* upload brs register */
    saa7146_write(dev, MC2, (MASK_08|MASK_24));
    return 0;
}
Esempio n. 2
0
static int vbi_open(struct saa7146_dev *dev, struct file *file)
{
	struct saa7146_fh *fh = file->private_data;
	struct saa7146_vv *vv = fh->dev->vv_data;

	u32 arbtr_ctrl	= saa7146_read(dev, PCI_BT_V1);
	int ret = 0;

	DEB_VBI("dev:%p, fh:%p\n", dev, fh);

	ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
	if (0 == ret) {
		DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
		return -EBUSY;
	}

	/* adjust arbitrition control for video dma 3 */
	arbtr_ctrl &= ~0x1f0000;
	arbtr_ctrl |=  0x1d0000;
	saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
	saa7146_write(dev, MC2, (MASK_04|MASK_20));

	videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
			    &dev->pci->dev, &dev->slock,
			    V4L2_BUF_TYPE_VBI_CAPTURE,
			    V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
			    sizeof(struct saa7146_buf),
			    file, &dev->v4l2_lock);

	vv->vbi_read_timeout.function = vbi_read_timeout;
	vv->vbi_read_timeout.data = (unsigned long)file;

	/* initialize the brs */
	if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
		saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
	} else {
		saa7146_write(dev, BRS_CTRL, 0x00000001);

		if (0 != (ret = vbi_workaround(dev))) {
			DEB_VBI("vbi workaround failed!\n");
			/* return ret;*/
		}
	}

	/* upload brs register */
	saa7146_write(dev, MC2, (MASK_08|MASK_24));
	return 0;
}