void psxsio_device::sio_interrupt()
{
verboselog( *this, 1, "sio_interrupt( %s )\n", tag() );
m_status |= SIO_STATUS_IRQ;
m_irq_handler(1);
}
static void avr8_disable_spi(running_machine &machine)
{
// TODO
verboselog(machine, 0, "avr8_disable_spi: TODO\n");
}
static void avr8_spi_update_clock_polarity(running_machine &machine)
{
// TODO
craft_state *state = machine.driver_data<craft_state>();
verboselog(machine, 0, "avr8_spi_update_clock_polarity: TODO; SCK is Active-%s\n", AVR8_SPCR_CPOL ? "Low" : "High");
}
static WRITE8_DEVICE_HANDLER( s3c2410_nand_data_w )
{
palmz22_state *state = space.machine().driver_data<palmz22_state>();
verboselog( space.machine(), 9, "s3c2410_nand_data_w %02X\n", data);
state->m_nand->data_w(data);
}
void ds2401_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch(id) {
case TIMER_RESET:
verboselog(1, "timer_reset\n");
state = STATE_RESET;
timer_reset->adjust(attotime::never);
break;
case TIMER_MAIN:
switch(state) {
case STATE_RESET1:
verboselog(2, "timer_main state_reset1 %d\n", rx);
tx = false;
state = STATE_RESET2;
timer_main->adjust(t_pdl);
break;
case STATE_RESET2:
verboselog(2, "timer_main state_reset2 %d\n", rx);
tx = true;
bit = 0;
shift = 0;
state = STATE_COMMAND;
break;
case STATE_COMMAND:
verboselog(2, "timer_main state_command %d\n", rx);
shift >>= 1;
if(rx)
shift |= 0x80;
bit++;
if(bit == 8) {
switch(shift) {
case COMMAND_READROM:
verboselog(1, "timer_main readrom\n");
bit = 0;
byte = 0;
state = STATE_READROM;
break;
default:
verboselog(0, "timer_main command not handled %02x\n", shift);
state = STATE_IDLE;
break;
}
}
break;
case STATE_READROM:
tx = true;
if(byte == SIZE_DATA) {
verboselog(1, "timer_main readrom finished\n");
state = STATE_IDLE;
} else {
verboselog(2, "timer_main readrom window closed\n");
}
break;
default:
verboselog(0, "timer_main state not handled: %d\n", state);
break;
}
}
}
void x76f041_init( int chip, UINT8 *data )
{
int offset;
struct x76f041_chip *c;
if( chip >= X76F041_MAXCHIP )
{
verboselog( 0, "x76f041_init( %d ) chip out of range\n", chip );
return;
}
c = &x76f041[ chip ];
if( data == NULL )
{
data = auto_malloc(
SIZE_RESPONSE_TO_RESET +
SIZE_READ_PASSWORD +
SIZE_WRITE_PASSWORD +
SIZE_CONFIGURATION_PASSWORD +
SIZE_CONFIGURATION_REGISTERS +
SIZE_DATA );
}
c->cs = 0;
c->rst = 0;
c->scl = 0;
c->sdaw = 0;
c->sdar = 0;
c->state = STATE_STOP;
c->shift = 0;
c->bit = 0;
c->byte = 0;
c->command = 0;
c->address = 0;
memset( c->write_buffer, 0, SIZE_WRITE_BUFFER );
offset = 0;
c->response_to_reset = &data[ offset ]; offset += SIZE_RESPONSE_TO_RESET;
c->write_password = &data[ offset ]; offset += SIZE_WRITE_PASSWORD;
c->read_password = &data[ offset ]; offset += SIZE_READ_PASSWORD;
c->configuration_password = &data[ offset ]; offset += SIZE_CONFIGURATION_PASSWORD;
c->configuration_registers = &data[ offset ]; offset += SIZE_CONFIGURATION_REGISTERS;
c->data = &data[ offset ]; offset += SIZE_DATA;
state_save_register_item( "x76f041", chip, c->cs );
state_save_register_item( "x76f041", chip, c->rst );
state_save_register_item( "x76f041", chip, c->scl );
state_save_register_item( "x76f041", chip, c->sdaw );
state_save_register_item( "x76f041", chip, c->sdar );
state_save_register_item( "x76f041", chip, c->state );
state_save_register_item( "x76f041", chip, c->shift );
state_save_register_item( "x76f041", chip, c->bit );
state_save_register_item( "x76f041", chip, c->byte );
state_save_register_item( "x76f041", chip, c->command );
state_save_register_item( "x76f041", chip, c->address );
state_save_register_item_array( "x76f041", chip, c->write_buffer );
state_save_register_item_pointer( "x76f041", chip, c->response_to_reset, SIZE_RESPONSE_TO_RESET );
state_save_register_item_pointer( "x76f041", chip, c->write_password, SIZE_WRITE_PASSWORD );
state_save_register_item_pointer( "x76f041", chip, c->read_password, SIZE_READ_PASSWORD );
state_save_register_item_pointer( "x76f041", chip, c->configuration_password, SIZE_CONFIGURATION_PASSWORD );
state_save_register_item_pointer( "x76f041", chip, c->configuration_registers, SIZE_CONFIGURATION_REGISTERS );
state_save_register_item_pointer( "x76f041", chip, c->data, SIZE_DATA );
}
static WRITE32_HANDLER( ps_rtc_w )
{
pockstat_state *state = space->machine().driver_data<pockstat_state>();
switch(offset)
{
case 0x0000/4:
verboselog(space->machine(), 0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
COMBINE_DATA(&state->m_rtc_regs.mode);
break;
case 0x0004/4:
verboselog(space->machine(), 0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
if(state->m_rtc_regs.control == 1 && data == 1)
{
switch(state->m_rtc_regs.mode >> 1)
{
case 0: // Seconds
state->m_rtc_regs.time += 0x00000001;
if((state->m_rtc_regs.time & 0x0000000f) == 0x0000000a)
{
state->m_rtc_regs.time &= 0xfffffff0;
state->m_rtc_regs.time += 0x00000010;
if((state->m_rtc_regs.time & 0x000000ff) == 0x00000060)
{
state->m_rtc_regs.time &= 0xffffff00;
}
}
break;
case 1: // Minutes
state->m_rtc_regs.time += 0x00000100;
if((state->m_rtc_regs.time & 0x00000f00) == 0x00000a00)
{
state->m_rtc_regs.time &= 0xfffff0ff;
state->m_rtc_regs.time += 0x00001000;
if((state->m_rtc_regs.time & 0x0000ff00) == 0x00006000)
{
state->m_rtc_regs.time &= 0xffff00ff;
}
}
break;
case 2: // Hours
state->m_rtc_regs.time += 0x00010000;
if((state->m_rtc_regs.time & 0x00ff0000) == 0x00240000)
{
state->m_rtc_regs.time &= 0xff00ffff;
}
else if((state->m_rtc_regs.time & 0x000f0000) == 0x000a0000)
{
state->m_rtc_regs.time &= 0xfff0ffff;
state->m_rtc_regs.time += 0x00100000;
}
break;
case 3: // Day of the week
state->m_rtc_regs.time += 0x01000000;
if((state->m_rtc_regs.time & 0x0f000000) == 0x08000000)
{
state->m_rtc_regs.time &= 0xf0ffffff;
state->m_rtc_regs.time |= 0x01000000;
}
break;
case 4: // Day
state->m_rtc_regs.date += 0x00000001;
if((state->m_rtc_regs.date & 0x000000ff) == 0x00000032)
{
state->m_rtc_regs.date &= 0xffffff00;
}
else if((state->m_rtc_regs.date & 0x0000000f) == 0x0000000a)
{
state->m_rtc_regs.date &= 0xfffffff0;
state->m_rtc_regs.date += 0x00000010;
}
break;
case 5: // Month
state->m_rtc_regs.date += 0x00000100;
if((state->m_rtc_regs.date & 0x0000ff00) == 0x00001300)
{
state->m_rtc_regs.date &= 0xffffff00;
state->m_rtc_regs.date |= 0x00000001;
}
else if((state->m_rtc_regs.date & 0x00000f00) == 0x00000a00)
{
state->m_rtc_regs.date &= 0xfffff0ff;
state->m_rtc_regs.date += 0x00001000;
}
break;
case 6: // Year (LSB)
state->m_rtc_regs.date += 0x00010000;
if((state->m_rtc_regs.date & 0x000f0000) == 0x000a0000)
{
state->m_rtc_regs.date &= 0xfff0ffff;
state->m_rtc_regs.date += 0x00100000;
if((state->m_rtc_regs.date & 0x00f00000) == 0x00a00000)
{
state->m_rtc_regs.date &= 0xff00ffff;
}
}
break;
case 7: // Year (MSB)
break;
}
state->m_rtc_regs.control = 0;
}
else if(state->m_rtc_regs.control == 0)
{
COMBINE_DATA(&state->m_rtc_regs.control);
}
break;
default:
verboselog(space->machine(), 0, "ps_rtc_w: Unknown Register %08x = %08x & %08x\n", 0x0b800000 + (offset << 2), data, mem_mask );
break;
}
static READ8_HANDLER(sgi_ip2_mbp_r)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_mbp_r: %02x\n", state->m_mbp);
return state->m_mbp;
}
static WRITE8_HANDLER(sgi_ip2_mbp_w)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_mbp_w: %02x\n", data);
state->m_mbp = data;
}
static READ16_HANDLER(sgi_ip2_swtch_r)
{
verboselog(space->machine(), 0, "sgi_ip2_swtch_r: %04x\n", input_port_read(space->machine(), "SWTCH"));
return input_port_read(space->machine(), "SWTCH");
}
static WRITE8_HANDLER(sgi_ip2_clock_data_w)
{
verboselog(space->machine(), 1, "sgi_ip2_clock_data_w: %02x\n", data);
mc146818_device *rtc = space->machine().device<mc146818_device>("rtc");
rtc->write(*space, 0, data);
}
static READ8_HANDLER(sgi_ip2_m_but_r)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_m_but_r: %02x\n", state->m_mbut | BOARD_REV1);
return state->m_mbut | BOARD_REV1;
}
void zs01_init( int chip, unsigned char *data, zs01_write_handler write, zs01_read_handler read, unsigned char *ds2401 )
{
int offset;
struct zs01_chip *c;
if( chip >= ZS01_MAXCHIP )
{
verboselog( 0, "zs01_init( %d ) chip out of range\n", chip );
return;
}
c = &zs01[ chip ];
if( data == NULL )
{
data = auto_malloc(
SIZE_RESPONSE_TO_RESET +
SIZE_KEY +
SIZE_KEY +
SIZE_DATA );
}
if( ds2401 == NULL )
{
ds2401 = auto_malloc( SIZE_DATA_BUFFER );
}
c->cs = 0;
c->rst = 0;
c->scl = 0;
c->sdaw = 0;
c->sdar = 0;
c->state = STATE_STOP;
c->shift = 0;
c->bit = 0;
c->byte = 0;
memset( c->write_buffer, 0, SIZE_WRITE_BUFFER );
memset( c->read_buffer, 0, SIZE_READ_BUFFER );
memset( c->response_key, 0, SIZE_KEY );
offset = 0;
c->response_to_reset = &data[ offset ]; offset += SIZE_RESPONSE_TO_RESET;
c->command_key = &data[ offset ]; offset += SIZE_KEY;
c->data_key = &data[ offset ]; offset += SIZE_KEY;
c->data = &data[ offset ]; offset += SIZE_DATA;
c->ds2401 = ds2401;
c->write = write;
c->read = read;
state_save_register_item( "zs01", chip, c->cs );
state_save_register_item( "zs01", chip, c->rst );
state_save_register_item( "zs01", chip, c->scl );
state_save_register_item( "zs01", chip, c->sdaw );
state_save_register_item( "zs01", chip, c->sdar );
state_save_register_item( "zs01", chip, c->state );
state_save_register_item( "zs01", chip, c->shift );
state_save_register_item( "zs01", chip, c->bit );
state_save_register_item( "zs01", chip, c->byte );
state_save_register_item_array( "zs01", chip, c->write_buffer );
state_save_register_item_array( "zs01", chip, c->read_buffer );
state_save_register_item_array( "zs01", chip, c->response_key );
state_save_register_item_pointer( "zs01", chip, c->response_to_reset, SIZE_RESPONSE_TO_RESET );
state_save_register_item_pointer( "zs01", chip, c->command_key, SIZE_KEY );
state_save_register_item_pointer( "zs01", chip, c->data_key, SIZE_DATA );
}
void zs01_scl_write( int chip, int scl )
{
struct zs01_chip *c;
if( chip >= ZS01_MAXCHIP )
{
verboselog( 0, "zs01_scl_write( %d ) chip out of range\n", chip );
return;
}
c = &zs01[ chip ];
if( c->scl != scl )
{
verboselog( 2, "zs01(%d) scl=%d\n", chip, scl );
}
if( c->cs == 0 )
{
switch( c->state )
{
case STATE_STOP:
break;
case STATE_RESPONSE_TO_RESET:
if( c->scl != 0 && scl == 0 )
{
if( c->bit == 0 )
{
c->shift = c->response_to_reset[ c->byte ];
verboselog( 1, "zs01(%d) <- response_to_reset[%d]: %02x\n", chip, c->byte, c->shift );
}
c->sdar = ( c->shift >> 7 ) & 1;
c->shift <<= 1;
c->bit++;
if( c->bit == 8 )
{
c->bit = 0;
c->byte++;
if( c->byte == 4 )
{
c->sdar = 1;
verboselog( 1, "zs01(%d) goto stop\n", chip );
c->state = STATE_STOP;
}
}
}
break;
case STATE_LOAD_COMMAND:
if( c->scl == 0 && scl != 0 )
{
if( c->bit < 8 )
{
verboselog( 2, "zs01(%d) clock\n", chip );
c->shift <<= 1;
if( c->sdaw != 0 )
{
c->shift |= 1;
}
c->bit++;
}
else
{
c->sdar = 0;
switch( c->state )
{
case STATE_LOAD_COMMAND:
c->write_buffer[ c->byte ] = c->shift;
verboselog( 2, "zs01(%d) -> write_buffer[%d]: %02x\n", chip, c->byte, c->write_buffer[ c->byte ] );
c->byte++;
if( c->byte == SIZE_WRITE_BUFFER )
{
UINT16 crc;
zs01_decrypt( c->write_buffer, c->write_buffer, SIZE_WRITE_BUFFER, c->command_key, 0xff );
if( ( c->write_buffer[ 0 ] & 4 ) != 0 )
{
zs01_decrypt2( &c->write_buffer[ 2 ], &c->write_buffer[ 2 ], SIZE_DATA_BUFFER, c->data_key, 0x00 );
}
crc = zs01_crc( c->write_buffer, 10 );
if( crc == ( ( c->write_buffer[ 10 ] << 8 ) | c->write_buffer[ 11 ] ) )
{
verboselog( 1, "zs01(%d) -> command: %02x\n", chip, c->write_buffer[ 0 ] );
verboselog( 1, "zs01(%d) -> address: %02x\n", chip, c->write_buffer[ 1 ] );
verboselog( 1, "zs01(%d) -> data: %02x%02x%02x%02x%02x%02x%02x%02x\n", chip,
c->write_buffer[ 2 ], c->write_buffer[ 3 ], c->write_buffer[ 4 ], c->write_buffer[ 5 ],
c->write_buffer[ 6 ], c->write_buffer[ 7 ], c->write_buffer[ 8 ], c->write_buffer[ 9 ] );
verboselog( 1, "zs01(%d) -> crc: %02x%02x\n", chip, c->write_buffer[ 10 ], c->write_buffer[ 11 ] );
switch( c->write_buffer[ 0 ] & 1 )
{
case COMMAND_WRITE:
memcpy( &c->data[ zs01_data_offset( c ) ], &c->write_buffer[ 2 ], SIZE_DATA_BUFFER );
/* todo: find out what should be returned. */
memset( &c->read_buffer[ 0 ], 0, SIZE_WRITE_BUFFER );
break;
case COMMAND_READ:
/* todo: find out what should be returned. */
memset( &c->read_buffer[ 0 ], 0, 2 );
switch( c->write_buffer[ 1 ] )
{
case 0xfd:
{
/* TODO: use read/write to talk to the ds2401, which will require a timer. */
int i;
for( i = 0; i < SIZE_DATA_BUFFER; i++ )
{
c->read_buffer[ 2 + i ] = c->ds2401[ SIZE_DATA_BUFFER - i - 1 ];
}
}
break;
default:
memcpy( &c->read_buffer[ 2 ], &c->data[ zs01_data_offset( c ) ], SIZE_DATA_BUFFER );
break;
}
memcpy( c->response_key, &c->write_buffer[ 2 ], SIZE_KEY );
break;
}
}
else
{
verboselog( 0, "zs01(%d) bad crc\n", chip );
/* todo: find out what should be returned. */
memset( &c->read_buffer[ 0 ], 0xff, 2 );
}
verboselog( 1, "zs01(%d) <- status: %02x%02\n", chip,
c->read_buffer[ 0 ], c->read_buffer[ 1 ] );
verboselog( 1, "zs01(%d) <- data: %02x%02x%02x%02x%02x%02x%02x%02x\n", chip,
c->read_buffer[ 2 ], c->read_buffer[ 3 ], c->read_buffer[ 4 ], c->read_buffer[ 5 ],
c->read_buffer[ 6 ], c->read_buffer[ 7 ], c->read_buffer[ 8 ], c->read_buffer[ 9 ] );
crc = zs01_crc( c->read_buffer, 10 );
c->read_buffer[ 10 ] = crc >> 8;
c->read_buffer[ 11 ] = crc & 255;
zs01_encrypt( c->read_buffer, c->read_buffer, SIZE_READ_BUFFER, c->response_key, 0xff );
c->byte = 0;
c->state = STATE_READ_DATA;
}
break;
}
c->bit = 0;
c->shift = 0;
}
}
break;
case STATE_READ_DATA:
if( c->scl == 0 && scl != 0 )
{
if( c->bit < 8 )
{
if( c->bit == 0 )
{
switch( c->state )
{
case STATE_READ_DATA:
c->shift = c->read_buffer[ c->byte ];
verboselog( 2, "zs01(%d) <- read_buffer[%d]: %02x\n", chip, c->byte, c->shift );
break;
}
}
c->sdar = ( c->shift >> 7 ) & 1;
c->shift <<= 1;
c->bit++;
}
else
{
c->bit = 0;
c->sdar = 0;
if( c->sdaw == 0 )
{
verboselog( 2, "zs01(%d) ack <-\n", chip );
c->byte++;
if( c->byte == SIZE_READ_BUFFER )
{
c->byte = 0;
c->sdar = 1;
c->state = STATE_LOAD_COMMAND;
}
}
else
{
verboselog( 2, "zs01(%d) nak <-\n", chip );
}
}
}
break;
}
void cdislave_device::register_write(const UINT32 offset, const UINT16 data, const UINT16 mem_mask)
{
cdi_state *state = machine().driver_data<cdi_state>();
switch(offset)
{
case 0:
if(m_in_index)
{
verboselog(machine(), 0, "slave_w: Channel %d: %d = %02x\n", offset, m_in_index, data & 0x00ff );
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
if(m_in_index == m_in_count)
{
switch(m_in_buf[0])
{
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: // Update Mouse Position
set_mouse_position();
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
}
else
{
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
switch(data & 0x00ff)
{
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: case 0xdf:
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
verboselog(machine(), 0, "slave_w: Channel %d: Update Mouse Position (0x%02x)\n", offset, data & 0x00ff );
m_in_count = 3;
break;
default:
verboselog(machine(), 0, "slave_w: Channel %d: Unknown register: %02x\n", offset, data & 0x00ff );
m_in_index = 0;
break;
}
}
break;
case 1:
if(m_in_index)
{
verboselog(machine(), 0, "slave_w: Channel %d: %d = %02x\n", offset, m_in_index, data & 0x00ff );
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
if(m_in_index == m_in_count)
{
switch(m_in_buf[0])
{
case 0xf0: // Set Front Panel LCD
memcpy(m_lcd_state, m_in_buf + 1, 16);
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
default:
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
}
else
{
switch(data & 0x00ff)
{
default:
verboselog(machine(), 0, "slave_w: Channel %d: Unknown register: %02x\n", offset, data & 0x00ff );
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
break;
case 2:
if(m_in_index)
{
verboselog(machine(), 0, "slave_w: Channel %d: %d = %02x\n", offset, m_in_index, data & 0x00ff );
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
if(m_in_index == m_in_count)
{
switch(m_in_buf[0])
{
case 0xf0: // Set Front Panel LCD
memset(m_in_buf + 1, 0, 16);
m_in_count = 17;
break;
default:
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
}
else
{
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
switch(data & 0x00ff)
{
case 0x82: // Mute Audio
verboselog(machine(), 0, "slave_w: Channel %d: Mute Audio (0x82)\n", offset );
dmadac_enable(&state->m_dmadac[0], 2, 0);
m_in_index = 0;
m_in_count = 0;
//cdic->audio_sample_timer->adjust(attotime::never);
break;
case 0x83: // Unmute Audio
verboselog(machine(), 0, "slave_w: Channel %d: Unmute Audio (0x83)\n", offset );
dmadac_enable(&state->m_dmadac[0], 2, 1);
m_in_index = 0;
m_in_count = 0;
break;
case 0xf0: // Set Front Panel LCD
verboselog(machine(), 0, "slave_w: Channel %d: Set Front Panel LCD (0xf0)\n", offset );
m_in_count = 17;
break;
default:
verboselog(machine(), 0, "slave_w: Channel %d: Unknown register: %02x\n", offset, data & 0x00ff );
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
break;
case 3:
if(m_in_index)
{
verboselog(machine(), 0, "slave_w: Channel %d: %d = %02x\n", offset, m_in_index, data & 0x00ff );
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
if(m_in_index == m_in_count)
{
switch(m_in_buf[0])
{
case 0xb0: // Request Disc Status
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
prepare_readback(attotime::from_hz(4), 3, 4, 0xb0, 0x00, 0x02, 0x15, 0xb0);
break;
//case 0xb1: // Request Disc Base
//memset(m_in_buf, 0, 17);
//m_in_index = 0;
//m_in_count = 0;
//prepare_readback(attotime::from_hz(10000), 3, 4, 0xb1, 0x00, 0x00, 0x00, 0xb1);
//break;
default:
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
}
else
{
m_in_buf[m_in_index] = data & 0x00ff;
m_in_index++;
switch(data & 0x00ff)
{
case 0xb0: // Request Disc Status
verboselog(machine(), 0, "slave_w: Channel %d: Request Disc Status (0xb0)\n", offset );
m_in_count = 4;
break;
case 0xb1: // Request Disc Base
verboselog(machine(), 0, "slave_w: Channel %d: Request Disc Base (0xb1)\n", offset );
m_in_count = 4;
break;
case 0xf0: // Request SLAVE Revision
verboselog(machine(), 0, "slave_w: Channel %d: Request SLAVE Revision (0xf0)\n", offset );
prepare_readback(attotime::from_hz(10000), 2, 2, 0xf0, 0x32, 0x31, 0, 0xf0);
m_in_index = 0;
break;
case 0xf3: // Request Pointer Type
verboselog(machine(), 0, "slave_w: Channel %d: Request Pointer Type (0xf3)\n", offset );
m_in_index = 0;
prepare_readback(attotime::from_hz(10000), 2, 2, 0xf3, 1, 0, 0, 0xf3);
break;
case 0xf4: // Request Test Plug Status
verboselog(machine(), 0, "slave_w: Channel %d: Request Test Plug Status (0xf4)\n", offset );
m_in_index = 0;
prepare_readback(attotime::from_hz(10000), 2, 2, 0xf4, 0, 0, 0, 0xf4);
break;
case 0xf6: // Request NTSC/PAL Status
verboselog(machine(), 0, "slave_w: Channel %d: Request NTSC/PAL Status (0xf6)\n", offset );
prepare_readback(attotime::never, 2, 2, 0xf6, 2, 0, 0, 0xf6);
m_in_index = 0;
break;
case 0xf7: // Enable Input Polling
verboselog(machine(), 0, "slave_w: Channel %d: Activate Input Polling (0xf7)\n", offset );
m_polling_active = 1;
m_in_index = 0;
break;
case 0xfa: // Enable X-Bus Interrupts
verboselog(machine(), 0, "slave_w: Channel %d: X-Bus Interrupt Enable (0xfa)\n", offset );
m_xbus_interrupt_enable = 1;
m_in_index = 0;
break;
default:
verboselog(machine(), 0, "slave_w: Channel %d: Unknown register: %02x\n", offset, data & 0x00ff );
memset(m_in_buf, 0, 17);
m_in_index = 0;
m_in_count = 0;
break;
}
}
break;
}
}
static READ32_HANDLER(sgi_ip2_ptmap_r)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), state->m_ptmap[offset], mem_mask);
return state->m_ptmap[offset];
}
void psxirq_device::set( UINT32 bitmask )
{
verboselog( machine(), 2, "psx_irq_set %08x\n", bitmask );
n_irqdata |= bitmask;
psx_irq_update();
}
static WRITE32_HANDLER(sgi_ip2_ptmap_w)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
COMBINE_DATA(&state->m_ptmap[offset]);
}
void gp32_state::s3c240x_lcd_stop()
{
verboselog( machine(), 1, "LCD stop\n");
m_s3c240x_lcd_timer->adjust( attotime::never);
}
static READ16_HANDLER(sgi_ip2_stklmt_r)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_stklmt_r: %04x\n", state->m_stklmt);
return state->m_stklmt;
}
static WRITE8_DEVICE_HANDLER( s3c2410_nand_address_w )
{
palmz22_state *state = device->machine().driver_data<palmz22_state>();
verboselog( device->machine(), 9, "s3c2410_nand_address_w %02X\n", data);
state->m_nand->address_w(data);
}
static WRITE16_HANDLER(sgi_ip2_stklmt_w)
{
sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
verboselog(space->machine(), 0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
COMBINE_DATA(&state->m_stklmt);
}
void x76f100_scl_write( running_machine *machine, int chip, int scl )
{
struct x76f100_chip *c;
if( chip >= X76F100_MAXCHIP )
{
verboselog( machine, 0, "x76f100_scl_write( %d ) chip out of range\n", chip );
return;
}
c = &x76f100[ chip ];
if( c->scl != scl )
{
verboselog( machine, 2, "x76f100(%d) scl=%d\n", chip, scl );
}
if( c->cs == 0 )
{
switch( c->state )
{
case STATE_STOP:
break;
case STATE_RESPONSE_TO_RESET:
if( c->scl != 0 && scl == 0 )
{
if( c->bit == 0 )
{
c->shift = c->response_to_reset[ c->byte ];
verboselog( machine, 1, "x76f100(%d) <- response_to_reset[%d]: %02x\n", chip, c->byte, c->shift );
}
c->sdar = c->shift & 1;
c->shift >>= 1;
c->bit++;
if( c->bit == 8 )
{
c->bit = 0;
c->byte++;
if( c->byte == 4 )
{
c->byte = 0;
}
}
}
break;
case STATE_LOAD_COMMAND:
case STATE_LOAD_PASSWORD:
case STATE_VERIFY_PASSWORD:
case STATE_WRITE_DATA:
if( c->scl == 0 && scl != 0 )
{
if( c->bit < 8 )
{
verboselog( machine, 2, "x76f100(%d) clock\n", chip );
c->shift <<= 1;
if( c->sdaw != 0 )
{
c->shift |= 1;
}
c->bit++;
}
else
{
c->sdar = 0;
switch( c->state )
{
case STATE_LOAD_COMMAND:
c->command = c->shift;
verboselog( machine, 1, "x76f100(%d) -> command: %02x\n", chip, c->command );
/* todo: verify command is valid? */
c->state = STATE_LOAD_PASSWORD;
break;
case STATE_LOAD_PASSWORD:
verboselog( machine, 1, "x76f100(%d) -> password: %02x\n", chip, c->shift );
c->write_buffer[ c->byte++ ] = c->shift;
if( c->byte == SIZE_WRITE_BUFFER )
{
c->state = STATE_VERIFY_PASSWORD;
}
break;
case STATE_VERIFY_PASSWORD:
verboselog( machine, 1, "x76f100(%d) -> verify password: %02x\n", chip, c->shift );
/* todo: this should probably be handled as a command */
if( c->shift == COMMAND_ACK_PASSWORD )
{
/* todo: this should take 10ms before it returns ok. */
if( memcmp( x76f100_password( c ), c->write_buffer, SIZE_WRITE_BUFFER ) == 0 )
{
x76f100_password_ok( c );
}
else
{
c->sdar = 1;
}
}
break;
case STATE_WRITE_DATA:
verboselog( machine, 1, "x76f100(%d) -> data: %02x\n", chip, c->shift );
c->write_buffer[ c->byte++ ] = c->shift;
if( c->byte == SIZE_WRITE_BUFFER )
{
for( c->byte = 0; c->byte < SIZE_WRITE_BUFFER; c->byte++ )
{
c->data[ x76f100_data_offset( c ) ] = c->write_buffer[ c->byte ];
}
c->byte = 0;
verboselog( machine, 1, "x76f100(%d) data flushed\n", chip );
}
break;
}
c->bit = 0;
c->shift = 0;
}
}
break;
case STATE_READ_DATA:
if( c->scl == 0 && scl != 0 )
{
if( c->bit < 8 )
{
if( c->bit == 0 )
{
switch( c->state )
{
case STATE_READ_DATA:
c->shift = c->data[ x76f100_data_offset( c ) ];
verboselog( machine, 1, "x76f100(%d) <- data: %02x\n", chip, c->shift );
break;
}
}
c->sdar = ( c->shift >> 7 ) & 1;
c->shift <<= 1;
c->bit++;
}
else
{
c->bit = 0;
c->sdar = 0;
if( c->sdaw == 0 )
{
verboselog( machine, 2, "x76f100(%d) ack <-\n", chip );
c->byte++;
}
else
{
verboselog( machine, 2, "x76f100(%d) nak <-\n", chip );
}
}
}
break;
}
}
void psxirq_device::set( uint32_t bitmask )
{
verboselog( *this, 2, "psx_irq_set %08x\n", bitmask );
n_irqdata |= bitmask;
psx_irq_update();
}
static void avr8_interrupt_update(running_machine &machine, int source)
{
// TODO
verboselog(machine, 0, "avr8_interrupt_update: TODO; source interrupt is %d\n", source);
}
static UINT8 duarta_input(device_t *device)
{
verboselog(device->machine(), 0, "duarta_input\n");
return 0;
}
static void avr8_spi_update_masterslave_select(running_machine &machine)
{
// TODO
craft_state *state = machine.driver_data<craft_state>();
verboselog(machine, 0, "avr8_spi_update_masterslave_select: TODO; AVR is %s\n", AVR8_SPCR_MSTR ? "Master" : "Slave");
}
static void lcd_spi_init( running_machine &machine)
{
verboselog( machine, 5, "lcd_spi_init\n");
lcd_spi_reset( machine);
}
static void avr8_spi_update_clock_phase(running_machine &machine)
{
// TODO
craft_state *state = machine.driver_data<craft_state>();
verboselog(machine, 0, "avr8_spi_update_clock_phase: TODO; Sampling edge is %s\n", AVR8_SPCR_CPHA ? "Trailing" : "Leading");
}
void psxsio_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
{
verboselog( *this, 2, "sio tick\n" );
if( m_tx_bits == 0 &&
( m_control & SIO_CONTROL_TX_ENA ) != 0 &&
( m_status & SIO_STATUS_TX_EMPTY ) == 0 )
{
m_tx_bits = 8;
m_tx_shift = m_tx_data;
if( type() == PSX_SIO0 )
{
m_rx_bits = 8;
m_rx_shift = 0;
}
m_status |= SIO_STATUS_TX_EMPTY;
m_status |= SIO_STATUS_TX_RDY;
}
if( m_tx_bits != 0 )
{
if( type() == PSX_SIO0 )
{
m_sck_handler(0);
}
m_txd_handler( m_tx_shift & 1 );
m_tx_shift >>= 1;
m_tx_bits--;
if( type() == PSX_SIO0 )
{
m_sck_handler(1);
}
if( m_tx_bits == 0 &&
( m_control & SIO_CONTROL_TX_IENA ) != 0 )
{
sio_interrupt();
}
}
if( m_rx_bits != 0 )
{
m_rx_shift = ( m_rx_shift >> 1 ) | ( m_rxd << 7 );
m_rx_bits--;
if( m_rx_bits == 0 )
{
if( ( m_status & SIO_STATUS_RX_RDY ) != 0 )
{
m_status |= SIO_STATUS_OVERRUN;
}
else
{
m_rx_data = m_rx_shift;
m_status |= SIO_STATUS_RX_RDY;
}
if( ( m_control & SIO_CONTROL_RX_IENA ) != 0 )
{
sio_interrupt();
}
}
}
