// CHECK-LABEL: test_vsetq_vgetq_lane_f16 int test_vsetq_vgetq_lane_f16(float16x8_t a) { float16x8_t b; b = vsetq_lane_f16(3.5, a, 5); float16_t c = vgetq_lane_f16(b, 5); return (int)c; // CHECK: movz x{{[0-9]+}}, #3 }
float32_t test_vgetq_lane_f16(float16x8_t a) { // CHECK-LABEL: test_vgetq_lane_f16: // CHECK-NEXT: umov.h w8, v0[3] // CHECK-NEXT: fmov s0, w8 // CHECK-NEXT: fcvt s0, h0 // CHECK-NEXT: ret return vgetq_lane_f16(a, 3); }
// CHECK: test_vsetq_lane_f16_2 float16x8_t test_vsetq_lane_f16_2(float16x8_t v1) { float16_t a = vgetq_lane_f16(v1, 0); return vsetq_lane_f16(a, v1, 7); // CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[0] }
// CHECK: test_vgetq_lane_f16_2 float test_vgetq_lane_f16_2(float16x8_t v1) { float16_t a = vgetq_lane_f16(v1, 7); return (float)a; // CHECK: dup {{h[0-9]+}}, {{v[0-9]+}}.h[7] }
// CHECK-LABEL: define float @test_vgetq_lane_f16(<8 x half> %a) #0 { // CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16 // CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2 // CHECK: store <8 x half> %a, <8 x half>* [[__REINT_244]], align 16 // CHECK: [[TMP0:%.*]] = bitcast <8 x half>* [[__REINT_244]] to <8 x i16>* // CHECK: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 16 // CHECK: [[TMP2:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8> // CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16> // CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3 // CHECK: store i16 [[VGETQ_LANE]], i16* [[__REINT1_244]], align 2 // CHECK: [[TMP4:%.*]] = bitcast i16* [[__REINT1_244]] to half* // CHECK: [[TMP5:%.*]] = load half, half* [[TMP4]], align 2 // CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float // CHECK: ret float [[CONV]] float32_t test_vgetq_lane_f16(float16x8_t a) { return vgetq_lane_f16(a, 3); }