/** * vi_asic_reset - soft reset GPU * * @adev: amdgpu_device pointer * * Look up which blocks are hung and attempt * to reset them. * Returns 0 for success. */ static int vi_asic_reset(struct amdgpu_device *adev) { u32 reset_mask; reset_mask = vi_gpu_check_soft_reset(adev); if (reset_mask) vi_set_bios_scratch_engine_hung(adev, true); /* try soft reset */ vi_gpu_soft_reset(adev, reset_mask); reset_mask = vi_gpu_check_soft_reset(adev); /* try pci config reset */ if (reset_mask && amdgpu_hard_reset) vi_gpu_pci_config_reset(adev); reset_mask = vi_gpu_check_soft_reset(adev); if (!reset_mask) vi_set_bios_scratch_engine_hung(adev, false); return 0; }
/** * vi_asic_reset - soft reset GPU * * @adev: amdgpu_device pointer * * Look up which blocks are hung and attempt * to reset them. * Returns 0 for success. */ static int vi_asic_reset(struct amdgpu_device *adev) { vi_set_bios_scratch_engine_hung(adev, true); vi_gpu_pci_config_reset(adev); vi_set_bios_scratch_engine_hung(adev, false); return 0; }
/** * vi_asic_reset - soft reset GPU * * @adev: amdgpu_device pointer * * Look up which blocks are hung and attempt * to reset them. * Returns 0 for success. */ static int vi_asic_reset(struct amdgpu_device *adev) { int r; amdgpu_atombios_scratch_regs_engine_hung(adev, true); r = vi_gpu_pci_config_reset(adev); amdgpu_atombios_scratch_regs_engine_hung(adev, false); return r; }