static int init_dma(pci_bus_cookie *cookie)
{
addr_t temp;
uint8 val = in8(cookie->io_port + BM_STATUS_REG );
TRACE(("entering init_dma status = %d\n",val));
if (!( val &( BM_SR_MASK_DRV1 | BM_SR_MASK_DRV0 )))
{
TRACE(("BM_STATUS is wrong %d\n",val));
return -1;
}
cookie->prd_region_id = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "ide_prd_buf", (void **)&cookie->prd_buf_address,
REGION_ADDR_ANY_ADDRESS, 4096, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
cookie->stat_reg = in8( cookie->io_port + + BM_STATUS_REG );
cookie->stat_reg = cookie->stat_reg & 0xe0;
memset(cookie->prd_buf_address, 0, 4096);
vm_get_page_mapping(vm_get_kernel_aspace_id(), (addr_t)cookie->prd_buf_address, &cookie->prd_phy_address);
cookie->raw_buffer = (uint8*)0x80000;
vm_map_physical_memory(vm_get_kernel_aspace_id(), "test", (void *)&cookie->mapped_address, REGION_ADDR_ANY_ADDRESS,0x10000, LOCK_RW|LOCK_KERNEL, (addr_t)cookie->raw_buffer);
TRACE(("mapped address is %X\n",cookie->mapped_address));
return 0;
}
static int vesa_ioctl(dev_cookie cookie, int op, void *buf, size_t len)
{
int err = 0;
if(!vesa.enabled)
return ERR_NOT_FOUND;
switch(op) {
case IOCTL_DEVFS_GET_FRAMEBUFFER_INFO:
if(is_kernel_address(buf))
err = ERR_VM_BAD_USER_MEMORY;
else
err = user_memcpy(buf, &vesa.fb_info, sizeof(vesa.fb_info));
break;
case IOCTL_DEVFS_MAP_FRAMEBUFFER: {
aspace_id aid = vm_get_current_user_aspace_id();
region_id rid;
void *address;
if(is_kernel_address(buf)) {
err = ERR_VM_BAD_USER_MEMORY;
goto out;
}
// map the framebuffer into the user's address space
rid = vm_map_physical_memory(aid, "vesa_fb", &address, REGION_ADDR_ANY_ADDRESS,
vesa.phys_memory.size, LOCK_RW, vesa.phys_memory.start);
if(rid < 0) {
err = rid;
goto out;
}
// copy the new pointer back to the user
err = user_memcpy(buf, &address, sizeof(address));
if(err < 0) {
vm_delete_region(aid, rid);
goto out;
}
// return the region id as the return code
err = rid;
break;
}
default:
err = ERR_INVALID_ARGS;
}
out:
return err;
}
int arch_vm_init_endvm(kernel_args *ka)
{
region_id id;
void *ptr;
dprintf("arch_vm_init_endvm: entry\n");
// map 0 - 0xa0000 directly
id = vm_map_physical_memory(vm_get_kernel_aspace_id(), "dma_region", &ptr,
REGION_ADDR_ANY_ADDRESS, 0xa0000, LOCK_RW|LOCK_KERNEL, 0x0);
if(id < 0) {
panic("arch_vm_init_endvm: unable to map dma region\n");
return ERR_NO_MEMORY;
}
return 0;
}
status_t
arch_vm_init_end(kernel_args *args)
{
TRACE(("arch_vm_init_end(): %lu virtual ranges to keep:\n",
args->arch_args.num_virtual_ranges_to_keep));
for (int i = 0; i < (int)args->arch_args.num_virtual_ranges_to_keep; i++) {
addr_range &range = args->arch_args.virtual_ranges_to_keep[i];
TRACE((" start: %p, size: 0x%lx\n", (void*)range.start, range.size));
#if 0
// skip ranges outside the kernel address space
if (!IS_KERNEL_ADDRESS(range.start)) {
TRACE((" no kernel address, skipping...\n"));
continue;
}
phys_addr_t physicalAddress;
void *address = (void*)range.start;
if (vm_get_page_mapping(VMAddressSpace::KernelID(), range.start,
&physicalAddress) != B_OK)
panic("arch_vm_init_end(): No page mapping for %p\n", address);
area_id area = vm_map_physical_memory(VMAddressSpace::KernelID(),
"boot loader reserved area", &address,
B_EXACT_ADDRESS, range.size,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
physicalAddress, true);
if (area < 0) {
panic("arch_vm_init_end(): Failed to create area for boot loader "
"reserved area: %p - %p\n", (void*)range.start,
(void*)(range.start + range.size));
}
#endif
}
#if 0
// Throw away any address space mappings we've inherited from the boot
// loader and have not yet turned into an area.
vm_free_unused_boot_loader_range(0, 0xffffffff - B_PAGE_SIZE + 1);
#endif
return B_OK;
}
int rhine_init(rhine *r)
{
bigtime_t time;
int err = -1;
addr_t temp;
int i;
dprintf("rhine_init: r %p\n", r);
r->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rhine_region", (void **)&r->virt_base,
REGION_ADDR_ANY_ADDRESS, r->phys_size, LOCK_KERNEL|LOCK_RW, r->phys_base);
if(r->region < 0) {
dprintf("rhine_init: error creating memory mapped region\n");
err = -1;
goto err;
}
dprintf("rhine mapped at address 0x%lx\n", r->virt_base);
/* create regions for tx and rx descriptors */
r->rxdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_rxdesc", (void **)&r->rxdesc,
REGION_ADDR_ANY_ADDRESS, RXDESC_COUNT * sizeof(struct rhine_rx_desc), REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->rxdesc_phys = vtophys(r->rxdesc);
dprintf("rhine: rx descriptors at %p, phys 0x%x\n", r->rxdesc, r->rxdesc_phys);
r->txdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_txdesc", (void **)&r->txdesc,
REGION_ADDR_ANY_ADDRESS, TXDESC_COUNT * sizeof(struct rhine_tx_desc), REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txdesc_phys = vtophys(r->txdesc);
dprintf("rhine: tx descriptors at %p, phys 0x%x\n", r->txdesc, r->txdesc_phys);
r->reg_spinlock = 0;
/* stick all rx and tx buffers in a circular buffer */
for (i=0; i < RXDESC_COUNT; i++) {
RXDESC(r, i).status = 0;
RXDESC(r, i).framelen = 0;
RXDESC(r, i).buflen = 0;
RXDESC(r, i).ptr = 0;
if (i == RXDESC_COUNT-1)
RXDESC(r, i).next = RXDESC_PHYS(r, 0);
else
RXDESC(r, i).next = RXDESC_PHYS(r, i + 1);
}
// XXX do same for tx
r->rx_head = r->rx_tail = 0;
/* reset the chip */
time = system_time();
RHINE_WRITE_16(r, RHINE_CR0, 0x8000); // reset the chip
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
break;
}
} while(RHINE_READ_16(r, RHINE_CR0) & 0x8000);
if (RHINE_READ_16(r, RHINE_CR0) & 0x8000) {
dprintf("chip didn't reset, trying alternate method\n");
RHINE_SETBITS_8(r, RHINE_MISC_CR1, 0x40);
thread_snooze(10000);
}
/* read in the mac address */
RHINE_WRITE_8(r, RHINE_EECSR, RHINE_READ_8(r, RHINE_EECSR) | (1<<5));
r->mac_addr[0] = RHINE_READ_8(r, RHINE_PAR0);
r->mac_addr[1] = RHINE_READ_8(r, RHINE_PAR1);
r->mac_addr[2] = RHINE_READ_8(r, RHINE_PAR2);
r->mac_addr[3] = RHINE_READ_8(r, RHINE_PAR3);
r->mac_addr[4] = RHINE_READ_8(r, RHINE_PAR4);
r->mac_addr[5] = RHINE_READ_8(r, RHINE_PAR5);
dprintf("rhine: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
/* set up the rx state */
/* 64 byte fifo threshold, all physical/broadcast/multicast/small/error packets accepted */
RHINE_WRITE_8(r, RHINE_RCR, (0<<5) | (1<<4) | (1<<3) | (1<<2) | (1<<1) | (1<<0));
RHINE_WRITE_32(r, RHINE_RDA0, RXDESC_PHYS(r, r->rx_head));
/* set up tx state */
/* 64 byte fifo, default backup, default loopback mode */
RHINE_WRITE_8(r, RHINE_TCR, 0);
/* mask all interrupts */
RHINE_WRITE_16(r, RHINE_IMR0, 0);
/* clear all pending interrupts */
RHINE_WRITE_16(r, RHINE_ISR0, 0xffff);
/* set up the interrupt handler */
int_set_io_interrupt_handler(r->irq, &rhine_int, r, "rhine");
{
static uint8 buf[2048];
RXDESC(r, r->rx_tail).ptr = vtophys(buf);
RXDESC(r, r->rx_tail).buflen = sizeof(buf);
RXDESC(r, r->rx_tail).status = 0;
RXDESC(r, r->rx_tail).framelen = RHINE_RX_OWNER;
r->rx_tail++;
RHINE_WRITE_16(r, RHINE_CR0, (1<<1) | (1<<3) | (1<<6));
}
/* unmask all interrupts */
RHINE_WRITE_16(r, RHINE_IMR0, 0xffff);
#if 0
// try to reset the device
time = system_time();
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RESET);
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
err = -1;
goto err1;
}
} while((RTL_READ_8(r, RT_CHIPCMD) & RT_CMD_RESET));
// create a rx and tx buf
r->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_rxbuf", (void **)&r->rxbuf,
REGION_ADDR_ANY_ADDRESS, 64*1024 + 16, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_txbuf", (void **)&r->txbuf,
REGION_ADDR_ANY_ADDRESS, 8*1024, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
// set up the transmission buf and sem
r->tx_sem = sem_create(4, "rhine_txsem");
mutex_init(&r->lock, "rhine");
r->txbn = 0;
r->last_txbn = 0;
r->rx_sem = sem_create(0, "rhine_rxsem");
r->reg_spinlock = 0;
// set up the interrupt handler
int_set_io_interrupt_handler(r->irq, &rhine_int, r, "rhine");
// read the mac address
r->mac_addr[0] = RTL_READ_8(r, RT_IDR0);
r->mac_addr[1] = RTL_READ_8(r, RT_IDR0 + 1);
r->mac_addr[2] = RTL_READ_8(r, RT_IDR0 + 2);
r->mac_addr[3] = RTL_READ_8(r, RT_IDR0 + 3);
r->mac_addr[4] = RTL_READ_8(r, RT_IDR0 + 4);
r->mac_addr[5] = RTL_READ_8(r, RT_IDR0 + 5);
dprintf("rhine: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
// enable writing to the config registers
RTL_WRITE_8(r, RT_CFG9346, 0xc0);
// reset config 1
RTL_WRITE_8(r, RT_CONFIG1, 0);
// Enable receive and transmit functions
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
// Set Rx FIFO threashold to 256, Rx size to 64k+16, 256 byte DMA burst
RTL_WRITE_32(r, RT_RXCONFIG, 0x00009c00);
// Set Tx 256 byte DMA burst
RTL_WRITE_32(r, RT_TXCONFIG, 0x03000400);
// Turn off lan-wake and set the driver-loaded bit
RTL_WRITE_8(r, RT_CONFIG1, (RTL_READ_8(r, RT_CONFIG1) & ~0x30) | 0x20);
// Enable FIFO auto-clear
RTL_WRITE_8(r, RT_CONFIG4, RTL_READ_8(r, RT_CONFIG4) | 0x80);
// go back to normal mode
RTL_WRITE_8(r, RT_CFG9346, 0);
// Setup RX buffers
*(int *)r->rxbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->rxbuf, &temp);
dprintf("rx buffer will be at 0x%lx\n", temp);
RTL_WRITE_32(r, RT_RXBUF, temp);
// Setup TX buffers
dprintf("tx buffer (virtual) is at 0x%lx\n", r->txbuf);
*(int *)r->txbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->txbuf, &temp);
RTL_WRITE_32(r, RT_TXADDR0, temp);
RTL_WRITE_32(r, RT_TXADDR1, temp + 2*1024);
dprintf("first half of txbuf at 0x%lx\n", temp);
*(int *)(r->txbuf + 4*1024) = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->txbuf + 4*1024, &temp);
RTL_WRITE_32(r, RT_TXADDR2, temp);
RTL_WRITE_32(r, RT_TXADDR3, temp + 2*1024);
dprintf("second half of txbuf at 0x%lx\n", temp);
/*
RTL_WRITE_32(r, RT_TXSTATUS0, RTL_READ_32(r, RT_TXSTATUS0) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS1, RTL_READ_32(r, RT_TXSTATUS1) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS2, RTL_READ_32(r, RT_TXSTATUS2) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS3, RTL_READ_32(r, RT_TXSTATUS3) | 0xfffff000);
*/
// Reset RXMISSED counter
RTL_WRITE_32(r, RT_RXMISSED, 0);
// Enable receiving broadcast and physical match packets
// RTL_WRITE_32(r, RT_RXCONFIG, RTL_READ_32(r, RT_RXCONFIG) | 0x0000000a);
RTL_WRITE_32(r, RT_RXCONFIG, RTL_READ_32(r, RT_RXCONFIG) | 0x0000000f);
// Filter out all multicast packets
RTL_WRITE_32(r, RT_MAR0, 0);
RTL_WRITE_32(r, RT_MAR0 + 4, 0);
// Disable all multi-interrupts
RTL_WRITE_16(r, RT_MULTIINTR, 0);
RTL_WRITE_16(r, RT_INTRMASK, MYRT_INTS);
// RTL_WRITE_16(r, RT_INTRMASK, 0x807f);
// Enable RX/TX once more
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
RTL_WRITE_8(r, RT_CFG9346, 0);
#endif
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), r->region);
err:
return err;
}
int rtl8169_init(rtl8169 *r)
{
bigtime_t time;
int err = -1;
addr_t temp;
int i;
SHOW_FLOW(2, "rtl8169_init: r %p\n", r);
r->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rtl8169_region", (void **)&r->virt_base,
REGION_ADDR_ANY_ADDRESS, r->phys_size, LOCK_KERNEL|LOCK_RW, r->phys_base);
if(r->region < 0) {
SHOW_ERROR0(1, "rtl8169_init: error creating memory mapped region\n");
err = -1;
goto err;
}
SHOW_INFO(2, "rtl8169 mapped at address 0x%lx\n", r->virt_base);
/* create regions for tx and rx descriptors */
r->rxdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_rxdesc", (void **)&r->rxdesc,
REGION_ADDR_ANY_ADDRESS, NUM_RX_DESCRIPTORS * DESCRIPTOR_LEN, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->rxdesc_phys = vtophys(r->rxdesc);
SHOW_INFO(2, "rtl8169: rx descriptors at %p, phys 0x%x\n", r->rxdesc, r->rxdesc_phys);
r->txdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_txdesc", (void **)&r->txdesc,
REGION_ADDR_ANY_ADDRESS, NUM_TX_DESCRIPTORS * DESCRIPTOR_LEN, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txdesc_phys = vtophys(r->txdesc);
SHOW_INFO(2, "rtl8169: tx descriptors at %p, phys 0x%x\n", r->txdesc, r->txdesc_phys);
r->reg_spinlock = 0;
/* create a large tx and rx buffer for the descriptors to point to */
r->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_rxbuf", (void **)&r->rxbuf,
REGION_ADDR_ANY_ADDRESS, NUM_RX_DESCRIPTORS * BUFSIZE_PER_FRAME, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
r->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_txbuf", (void **)&r->txbuf,
REGION_ADDR_ANY_ADDRESS, NUM_TX_DESCRIPTORS * BUFSIZE_PER_FRAME, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
/* create a receive sem */
r->rx_sem = sem_create(0, "rtl8169 rx_sem");
/* transmit sem */
r->tx_sem = sem_create(1, "rtl8169 tx_sem");
/* reset the chip */
time = system_time();
RTL_WRITE_8(r, REG_CR, (1<<4)); // reset the chip, disable tx/rx
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
break;
}
} while(RTL_READ_8(r, REG_CR) & (1<<4));
/* read in the mac address */
r->mac_addr[0] = RTL_READ_8(r, REG_IDR0);
r->mac_addr[1] = RTL_READ_8(r, REG_IDR1);
r->mac_addr[2] = RTL_READ_8(r, REG_IDR2);
r->mac_addr[3] = RTL_READ_8(r, REG_IDR3);
r->mac_addr[4] = RTL_READ_8(r, REG_IDR4);
r->mac_addr[5] = RTL_READ_8(r, REG_IDR5);
SHOW_INFO(2, "rtl8169: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
/* some voodoo from BSD driver */
RTL_WRITE_16(r, REG_CCR, RTL_READ_16(r, REG_CCR));
RTL_SETBITS_16(r, REG_CCR, 0x3);
/* mask all interrupts */
RTL_WRITE_16(r, REG_IMR, 0);
/* set up the tx/rx descriptors */
rtl8169_setup_descriptors(r);
/* enable tx/rx */
RTL_SETBITS_8(r, REG_CR, (1<<3)|(1<<2));
/* set up the rx state */
/* 1024 byte dma threshold, 1024 dma max burst, CRC calc 8 byte+, accept all packets */
RTL_WRITE_32(r, REG_RCR, (1<<16) | (6<<13) | (6<<8) | (0xf << 0));
RTL_SETBITS_16(r, REG_CCR, (1<<5)); // rx checksum enable
RTL_WRITE_16(r, REG_RMS, 1518); // rx mtu
/* set up the tx state */
RTL_WRITE_32(r, REG_TCR, (RTL_READ_32(r, REG_TCR) & ~0x1ff) | (6<<8)); // 1024 max burst dma
RTL_WRITE_8(r, REG_MTPS, 0x3f); // max tx packet size (must be careful to not actually transmit more than mtu)
/* set up the interrupt handler */
int_set_io_interrupt_handler(r->irq, &rtl8169_int, r, "rtl8169");
/* clear all pending interrupts */
RTL_WRITE_16(r, REG_ISR, 0xffff);
/* unmask interesting interrupts */
RTL_WRITE_16(r, REG_IMR, IMR_SYSERR | IMR_LINKCHG | IMR_TER | IMR_TOK | IMR_RER | IMR_ROK | IMR_RXOVL);
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), r->region);
err:
return err;
}
static int find_and_map(void)
{
int err;
pci_module_hooks *pci;
pci_info pinfo;
aspace_id kai = vm_get_kernel_aspace_id();
int i;
bool foundit;
if(module_get(PCI_BUS_MODULE_NAME, 0, (void **)&pci) < 0) {
dprintf("vmware: no pci bus found..\n");
err = ERR_NOT_FOUND;
goto error0;
}
foundit = false;
for(i = 0; pci->get_nth_pci_info(i, &pinfo) >= NO_ERROR; i++) {
dprintf("vmware: looking at 0x%x:0x%x\n", pinfo.vendor_id, pinfo.device_id);
if(pinfo.vendor_id == PCI_VENDOR_ID_VMWARE &&
(pinfo.device_id == PCI_DEVICE_ID_VMWARE_SVGA2 || pinfo.device_id == PCI_DEVICE_ID_VMWARE_SVGA)) {
foundit = true;
break;
}
}
if(!foundit) {
dprintf("vmware: didn't find device on pci bus\n");
err = ERR_NOT_FOUND;
goto error0;
}
switch(pinfo.device_id) {
case PCI_DEVICE_ID_VMWARE_SVGA:
dprintf("vmware SVGA device detected at pci %d:%d:%d\n", pinfo.bus, pinfo.device, pinfo.function);
vcons.index_port = SVGA_LEGACY_BASE_PORT + SVGA_INDEX_PORT * 4;
vcons.value_port = SVGA_LEGACY_BASE_PORT + SVGA_VALUE_PORT * 4;
break;
case PCI_DEVICE_ID_VMWARE_SVGA2:
dprintf("vmware SVGA2 device detected at pci %d:%d:%d\n", pinfo.bus, pinfo.device, pinfo.function);
vcons.index_port = pinfo.u.h0.base_registers[0] + SVGA_INDEX_PORT;
vcons.value_port = pinfo.u.h0.base_registers[0] + SVGA_VALUE_PORT;
break;
}
vcons.fb_phys_base = pinfo.u.h0.base_registers[1];
vcons.fb_size = MIN(pinfo.u.h0.base_register_sizes[1], SVGA_FB_MAX_SIZE);
vcons.fifo_phys_base = pinfo.u.h0.base_registers[2];
vcons.fifo_size = MIN(pinfo.u.h0.base_register_sizes[2], SVGA_MEM_SIZE);
dprintf("vmware: index port 0x%x, value port 0x%x\n", vcons.index_port, vcons.value_port);
dprintf("vmware: phys base 0x%x, size 0x%X\n", vcons.fb_phys_base, vcons.fb_size);
dprintf("vmware: fifo phys base 0x%x, fifo size 0x%X\n", vcons.fifo_phys_base, vcons.fifo_size);
vcons.fb_region = vm_map_physical_memory(kai, "vmw:fb", (void **)&vcons.fb_base, REGION_ADDR_ANY_ADDRESS, vcons.fb_size, LOCK_KERNEL | LOCK_RW, vcons.fb_phys_base);
if (vcons.fb_region < 0)
{
err = vcons.fb_region;
dprintf("Error mapping frame buffer: %x\n", err);
goto error0;
}
vcons.fifo_region = vm_map_physical_memory(kai, "vmw:fifo", (void **)&vcons.fifo_base, REGION_ADDR_ANY_ADDRESS, vcons.fifo_size, LOCK_KERNEL | LOCK_RW, vcons.fifo_phys_base);
if (vcons.fifo_region < 0)
{
err = vcons.fifo_region;
dprintf("Error mapping vmw::fifo: %x\n", err);
goto error1;
}
// XXX this makes the emulation unhappy (crashes vmware)
// out_reg(SVGA_REG_ID, SVGA_ID_2);
// vcons.svga_id = in_reg(SVGA_REG_ID);
// dprintf("vmware: svga version %d\n", vcons.svga_id);
vcons.bits_per_pixel = in_reg(SVGA_REG_BITS_PER_PIXEL);
dprintf("vmware: bpp %d\n", vcons.bits_per_pixel);
err = NO_ERROR;
goto error0;
// unmap vcons.fifo_region
vm_delete_region(kai, vcons.fifo_region);
error1:
// unmap vcons.fb_region
vm_delete_region(kai, vcons.fb_region);
error0:
return err;
}
int rtl8139_init(rtl8139 *rtl)
{
bigtime_t time;
int err = -1;
addr_t temp;
dprintf("rtl8139_init: rtl %p\n", rtl);
rtl->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rtl8139_region", (void **)&rtl->virt_base,
REGION_ADDR_ANY_ADDRESS, rtl->phys_size, LOCK_KERNEL|LOCK_RW, rtl->phys_base);
if(rtl->region < 0) {
dprintf("rtl8139_init: error creating memory mapped region\n");
err = -1;
goto err;
}
dprintf("rtl8139 mapped at address 0x%lx\n", rtl->virt_base);
// try to reset the device
time = system_time();
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RESET);
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
err = -1;
goto err1;
}
} while((RTL_READ_8(rtl, RT_CHIPCMD) & RT_CMD_RESET));
// create a rx and tx buf
rtl->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8139_rxbuf", (void **)&rtl->rxbuf,
REGION_ADDR_ANY_ADDRESS, 64*1024 + 16, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
rtl->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8139_txbuf", (void **)&rtl->txbuf,
REGION_ADDR_ANY_ADDRESS, 8*1024, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
// set up the transmission buf and sem
rtl->tx_sem = sem_create(4, "rtl8139_txsem");
mutex_init(&rtl->lock, "rtl8139");
rtl->txbn = 0;
rtl->last_txbn = 0;
rtl->rx_sem = sem_create(0, "rtl8139_rxsem");
rtl->reg_spinlock = 0;
// set up the interrupt handler
int_set_io_interrupt_handler(rtl->irq, &rtl8139_int, rtl, "rtl8139");
// read the mac address
rtl->mac_addr[0] = RTL_READ_8(rtl, RT_IDR0);
rtl->mac_addr[1] = RTL_READ_8(rtl, RT_IDR0 + 1);
rtl->mac_addr[2] = RTL_READ_8(rtl, RT_IDR0 + 2);
rtl->mac_addr[3] = RTL_READ_8(rtl, RT_IDR0 + 3);
rtl->mac_addr[4] = RTL_READ_8(rtl, RT_IDR0 + 4);
rtl->mac_addr[5] = RTL_READ_8(rtl, RT_IDR0 + 5);
dprintf("rtl8139: mac addr %x:%x:%x:%x:%x:%x\n",
rtl->mac_addr[0], rtl->mac_addr[1], rtl->mac_addr[2],
rtl->mac_addr[3], rtl->mac_addr[4], rtl->mac_addr[5]);
// enable writing to the config registers
RTL_WRITE_8(rtl, RT_CFG9346, 0xc0);
// reset config 1
RTL_WRITE_8(rtl, RT_CONFIG1, 0);
// Enable receive and transmit functions
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
// Set Rx FIFO threashold to 256, Rx size to 64k+16, 256 byte DMA burst
RTL_WRITE_32(rtl, RT_RXCONFIG, 0x00009c00);
// Set Tx 256 byte DMA burst
RTL_WRITE_32(rtl, RT_TXCONFIG, 0x03000400);
// Turn off lan-wake and set the driver-loaded bit
RTL_WRITE_8(rtl, RT_CONFIG1, (RTL_READ_8(rtl, RT_CONFIG1) & ~0x30) | 0x20);
// Enable FIFO auto-clear
RTL_WRITE_8(rtl, RT_CONFIG4, RTL_READ_8(rtl, RT_CONFIG4) | 0x80);
// go back to normal mode
RTL_WRITE_8(rtl, RT_CFG9346, 0);
// Setup RX buffers
*(int *)rtl->rxbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->rxbuf, &temp);
dprintf("rx buffer will be at 0x%lx\n", temp);
RTL_WRITE_32(rtl, RT_RXBUF, temp);
// Setup TX buffers
dprintf("tx buffer (virtual) is at 0x%lx\n", rtl->txbuf);
*(int *)rtl->txbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->txbuf, &temp);
RTL_WRITE_32(rtl, RT_TXADDR0, temp);
RTL_WRITE_32(rtl, RT_TXADDR1, temp + 2*1024);
dprintf("first half of txbuf at 0x%lx\n", temp);
*(int *)(rtl->txbuf + 4*1024) = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->txbuf + 4*1024, &temp);
RTL_WRITE_32(rtl, RT_TXADDR2, temp);
RTL_WRITE_32(rtl, RT_TXADDR3, temp + 2*1024);
dprintf("second half of txbuf at 0x%lx\n", temp);
/*
RTL_WRITE_32(rtl, RT_TXSTATUS0, RTL_READ_32(rtl, RT_TXSTATUS0) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS1, RTL_READ_32(rtl, RT_TXSTATUS1) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS2, RTL_READ_32(rtl, RT_TXSTATUS2) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS3, RTL_READ_32(rtl, RT_TXSTATUS3) | 0xfffff000);
*/
// Reset RXMISSED counter
RTL_WRITE_32(rtl, RT_RXMISSED, 0);
// Enable receiving broadcast and physical match packets
// RTL_WRITE_32(rtl, RT_RXCONFIG, RTL_READ_32(rtl, RT_RXCONFIG) | 0x0000000a);
RTL_WRITE_32(rtl, RT_RXCONFIG, RTL_READ_32(rtl, RT_RXCONFIG) | 0x0000000f);
// Filter out all multicast packets
RTL_WRITE_32(rtl, RT_MAR0, 0);
RTL_WRITE_32(rtl, RT_MAR0 + 4, 0);
// Disable all multi-interrupts
RTL_WRITE_16(rtl, RT_MULTIINTR, 0);
RTL_WRITE_16(rtl, RT_INTRMASK, MYRT_INTS);
// RTL_WRITE_16(rtl, RT_INTRMASK, 0x807f);
// Enable RX/TX once more
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
RTL_WRITE_8(rtl, RT_CFG9346, 0);
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), rtl->region);
err:
return err;
}
