void ppg_desc_init()
{
ppg_info_t *ppg = &info->hrd.mem.ppg;
ppg_dsc_t *dsc = ppg->dsc;
offset_t end = info->hrd.mem.top;
offset_t addr = 0;
ppg->vmm.nr = 0;
ppg->vm.nr = 0;
while(addr < end)
{
dsc->addr = addr;
if(vmm_area(addr))
{
dsc->count = 1;
dsc->vmm = 1;
cdll_fill(ppg->vmm.list, dsc);
ppg->vmm.nr++;
}
else
{
cdll_fill(ppg->vm.list, dsc);
ppg->vm.nr++;
}
addr += PAGE_SIZE;
dsc++;
}
}
/*
** lmode: 1GB, 2MB and 4KB pages
** cr4.pse is ignored
** 1GB cpuid feature must be checked
*/
static inline
int pg_walk_lmode(cr3_reg_t *cr3,
offset_t vaddr, offset_t *paddr,
size_t *psz, int chk)
{
pml4e_t *pml4, *pml4e;
pdpe_t *pdp, *pdpe;
pde64_t *pd, *pde;
pte64_t *pt, *pte;
pml4 = (pml4e_t*)page_addr(cr3->pml4.addr);
if(chk && vmm_area(pml4))
{
debug(PG_W, "pml4 in vmm area\n");
return 0;
}
pml4e = &pml4[pml4_idx(vaddr)];
debug(PG_W, "pml4e @ 0x%X = %X\n", (offset_t)pml4e, pml4e->raw);
if(!pg_present(pml4e))
{
debug(PG_W, "pml4e not present\n");
return 0;
}
pdp = (pdpe_t*)page_addr(pml4e->addr);
if(chk && vmm_area(pdp))
{
debug(PG_W, "pdp in vmm area\n");
return 0;
}
pdpe = &pdp[pdp_idx(vaddr)];
debug(PG_W, "pdpe @ 0x%X = 0x%X\n", (offset_t)pdpe, pdpe->raw);
if(!pg_present(pdpe))
{
debug(PG_W, "pdpe not present\n");
return 0;
}
if(info->vmm.cpu.skillz.pg_1G && pg_large(pdpe))
{
*paddr = pg_1G_addr((offset_t)pdpe->page.addr) + pg_1G_offset(vaddr);
*psz = PG_1G_SIZE;
goto __prepare_addr;
}
pd = (pde64_t*)page_addr(pdpe->addr);
if(chk && vmm_area(pd))
{
debug(PG_W, "pd in vmm area\n");
return 0;
}
pde = &pd[pd64_idx(vaddr)];
debug(PG_W, "pde @ 0x%X = 0x%X\n", (offset_t)pde, pde->raw);
if(!pg_present(pde))
{
debug(PG_W, "pde not present\n");
return 0;
}
if(pg_large(pde))
{
*paddr = pg_2M_addr((offset_t)pde->page.addr) + pg_2M_offset(vaddr);
*psz = PG_2M_SIZE;
goto __prepare_addr;
}
pt = (pte64_t*)page_addr(pde->addr);
if(chk && vmm_area(pt))
{
debug(PG_W, "pt in vmm area\n");
return 0;
}
pte = &pt[pt64_idx(vaddr)];
debug(PG_W, "pte @ 0x%X = 0x%X\n", (offset_t)pte, pte->raw);
if(!pg_present(pte))
{
debug(PG_W, "pte not present\n");
return 0;
}
*paddr = pg_4K_addr((offset_t)pte->addr) + pg_4K_offset(vaddr);
*psz = PG_4K_SIZE;
__prepare_addr:
if(chk && vmm_area(*paddr))
{
debug(PG_W, "paddr 0x%x in vmm area\n", *paddr);
return 0;
}
debug(PG_W, "lmode vaddr 0x%X -> paddr 0x%X\n", vaddr, *paddr);
return 1;
}
/*
** pmode: 4MB and 4KB pages
** cr4.pse is used
*/
static inline
int pg_walk_pmode(cr3_reg_t *cr3,
offset_t _vaddr, offset_t *_paddr,
size_t *psz, int chk)
{
pde32_t *pd, *pde;
pte32_t *pt, *pte;
uint32_t paddr;
uint32_t vaddr = _vaddr & 0xffffffff;
pd = (pde32_t*)page_addr(cr3->addr);
if(chk && vmm_area(pd))
{
debug(PG_W, "pd in vmm area\n");
return 0;
}
pde = &pd[pd32_idx(vaddr)];
debug(PG_W, "pde @ 0x%X = 0x%x\n", (offset_t)pde, pde->raw);
if(!pg_present(pde))
{
debug(PG_W, "pde not present\n");
return 0;
}
if(__cr4.pse && pg_large(pde))
{
debug(PG_W, "large page found (pde->addr 0x%x)\n", (uint32_t)pde->page.addr);
paddr = pg_4M_addr((uint32_t)pde->page.addr) + pg_4M_offset(vaddr);
*psz = PG_4M_SIZE;
goto __prepare_addr;
}
pt = (pte32_t*)page_addr(pde->addr);
if(chk && vmm_area(pt))
{
debug(PG_W, "pt in vmm area\n");
return 0;
}
pte = &pt[pt32_idx(vaddr)];
debug(PG_W, "pte @ 0x%X = 0x%x\n", (offset_t)pte, pte->raw);
if(!pg_present(pte))
{
debug(PG_W, "pte not present\n");
return 0;
}
paddr = pg_4K_addr((uint32_t)pte->addr) + pg_4K_offset(vaddr);
*psz = PG_4K_SIZE;
__prepare_addr:
if(chk && vmm_area(paddr))
{
debug(PG_W, "paddr 0x%x in vmm area\n", paddr);
return 0;
}
debug(PG_W, "pmode vaddr 0x%x -> paddr 0x%x\n", vaddr, paddr);
*_paddr = (offset_t)paddr;
return 1;
}
/*
** pmode+pae: 2MB and 4KB pages
** cr4.pse is used
*/
static inline
int pg_walk_pmode_pae(cr3_reg_t *cr3,
offset_t _vaddr, offset_t *paddr,
size_t *psz, int chk)
{
pdpe_t *pdp, *pdpe;
pde64_t *pd, *pde;
pte64_t *pt, *pte;
uint32_t vaddr = _vaddr & 0xffffffff;
pdp = (pdpe_t*)pg_32B_addr((offset_t)cr3->pae.addr);
if(chk && vmm_area(pdp))
{
debug(PG_W, "pdp in vmm area\n");
return 0;
}
pdpe = &pdp[pdp_pae_idx(vaddr)];
debug(PG_W, "pdpe @ 0x%X = 0x%X\n", (offset_t)pdpe, pdpe->raw);
if(!pg_present(pdpe))
{
debug(PG_W, "pdpe not present\n");
return 0;
}
pd = (pde64_t*)page_addr(pdpe->pae.addr);
if(chk && vmm_area(pd))
{
debug(PG_W, "pd in vmm area\n");
return 0;
}
pde = &pd[pd64_idx(vaddr)];
debug(PG_W, "pde @ 0x%X = 0x%X\n", (offset_t)pde, pde->raw);
if(!pg_present(pde))
{
debug(PG_W, "pde not present\n");
return 0;
}
if(__cr4.pse && pg_large(pde))
{
*paddr = pg_2M_addr((offset_t)pde->page.addr) + pg_2M_offset(vaddr);
*psz = PG_2M_SIZE;
goto __prepare_addr;
}
pt = (pte64_t*)page_addr(pde->addr);
if(chk && vmm_area(pt))
{
debug(PG_W, "pt in vmm area\n");
return 0;
}
pte = &pt[pt64_idx(vaddr)];
debug(PG_W, "pte @ 0x%X = 0x%X\n", (offset_t)pte, pte->raw);
if(!pg_present(pte))
{
debug(PG_W, "pte not present\n");
return 0;
}
*paddr = pg_4K_addr((offset_t)pte->addr) + pg_4K_offset(vaddr);
*psz = PG_4K_SIZE;
__prepare_addr:
if(chk && vmm_area(*paddr))
{
debug(PG_W, "paddr 0x%x in vmm area\n", *paddr);
return 0;
}
debug(PG_W, "pae vaddr 0x%x -> paddr 0x%x\n", vaddr, *paddr);
return 1;
}
