static int __init generic_timer_clocksource_init(struct vmm_devtree_node *node)
{
struct vmm_clocksource *cs;
generic_timer_get_freq(node);
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
cs = vmm_zalloc(sizeof(struct vmm_clocksource));
if (!cs) {
return VMM_EFAIL;
}
cs->name = "gen-timer";
cs->rating = 400;
cs->read = &generic_counter_read;
cs->mask = VMM_CLOCKSOURCE_MASK(56);
vmm_clocks_calc_mult_shift(&cs->mult, &cs->shift,
generic_timer_hz, VMM_NSEC_PER_SEC, 10);
generic_timer_mult = cs->mult;
generic_timer_shift = cs->shift;
cs->priv = NULL;
return vmm_clocksource_register(cs);
}
int __init epit_clocksource_init(void)
{
int rc = VMM_ENODEV;
u32 clock;
struct vmm_devtree_node *node;
struct epit_clocksource *ecs;
/* find a epit compatible node */
node = vmm_devtree_find_compatible(NULL, NULL, "freescale,epit-timer");
if (!node) {
goto fail;
}
/* Read clock frequency from node */
rc = vmm_devtree_clock_frequency(node, &clock);
if (rc) {
goto fail;
}
/* allocate our struct */
ecs = vmm_zalloc(sizeof(struct epit_clocksource));
if (!ecs) {
rc = VMM_ENOMEM;
goto fail;
}
/* Map timer registers */
rc = vmm_devtree_regmap(node, &ecs->base, 0);
if (rc) {
goto regmap_fail;
}
/* Setup clocksource */
ecs->clksrc.name = node->name;
ecs->clksrc.rating = 300;
ecs->clksrc.read = epit_clksrc_read;
ecs->clksrc.mask = VMM_CLOCKSOURCE_MASK(32);
vmm_clocks_calc_mult_shift(&ecs->clksrc.mult,
&ecs->clksrc.shift,
clock, VMM_NSEC_PER_SEC, 10);
ecs->clksrc.priv = ecs;
/* Register clocksource */
rc = vmm_clocksource_register(&ecs->clksrc);
if (rc) {
goto register_fail;
}
return VMM_OK;
register_fail:
vmm_devtree_regunmap(node, ecs->base, 0);
regmap_fail:
vmm_free(ecs);
fail:
return rc;
}
int __init generic_timer_clocksource_init(void)
{
int rc;
struct vmm_clocksource *cs;
struct vmm_devtree_node *node;
node = vmm_devtree_find_matching(NULL, generic_timer_match);
if (!node) {
return VMM_ENODEV;
}
if (generic_timer_hz == 0) {
rc = vmm_devtree_clock_frequency(node, &generic_timer_hz);
if (rc) {
/* Use preconfigured counter frequency
* in absence of dts node
*/
generic_timer_hz =
generic_timer_reg_read(GENERIC_TIMER_REG_FREQ);
} else {
if (generic_timer_freq_writeable()) {
/* Program the counter frequency
* as per the dts node
*/
generic_timer_reg_write(GENERIC_TIMER_REG_FREQ,
generic_timer_hz);
}
}
}
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
cs = vmm_zalloc(sizeof(struct vmm_clocksource));
if (!cs) {
return VMM_EFAIL;
}
cs->name = "gen-timer";
cs->rating = 400;
cs->read = &generic_counter_read;
cs->mask = VMM_CLOCKSOURCE_MASK(56);
vmm_clocks_calc_mult_shift(&cs->mult, &cs->shift,
generic_timer_hz, VMM_NSEC_PER_SEC, 10);
cs->priv = NULL;
return vmm_clocksource_register(cs);
}
static int __init bcm2835_clocksource_init(struct vmm_devtree_node *node)
{
int rc;
u32 clock;
struct bcm2835_clocksource *bcs;
/* Read clock frequency */
rc = vmm_devtree_clock_frequency(node, &clock);
if (rc) {
return rc;
}
bcs = vmm_zalloc(sizeof(struct bcm2835_clocksource));
if (!bcs) {
return VMM_ENOMEM;
}
/* Map timer registers */
rc = vmm_devtree_regmap(node, &bcs->base, 0);
if (rc) {
vmm_free(bcs);
return rc;
}
bcs->system_clock = (void *)(bcs->base + REG_COUNTER_LO);
/* Setup clocksource */
bcs->clksrc.name = "bcm2835_timer";
bcs->clksrc.rating = 300;
bcs->clksrc.read = bcm2835_clksrc_read;
bcs->clksrc.mask = VMM_CLOCKSOURCE_MASK(32);
vmm_clocks_calc_mult_shift(&bcs->clksrc.mult,
&bcs->clksrc.shift,
clock, VMM_NSEC_PER_SEC, 10);
bcs->clksrc.priv = bcs;
/* Register clocksource */
rc = vmm_clocksource_register(&bcs->clksrc);
if (rc) {
vmm_devtree_regunmap(node, bcs->base, 0);
vmm_free(bcs);
return rc;
}
return VMM_OK;
}
int __init s32k_clocksource_init(physical_addr_t base)
{
int rc;
virtual_addr_t synct_base;
/* Map registers */
synct_base = vmm_host_iomap(base, 0x1000);
/* Save pointer to registers in clocksource private */
s32k_clksrc.priv = (void *)synct_base;
/* Compute mult for clocksource */
vmm_clocks_calc_mult_shift(&s32k_clksrc.mult, &s32k_clksrc.shift,
S32K_FREQ_HZ, VMM_NSEC_PER_SEC, 10);
/* Register clocksource */
if ((rc = vmm_clocksource_register(&s32k_clksrc))) {
return rc;
}
return VMM_OK;
}
static int __cpuinit twd_clockchip_init(struct vmm_devtree_node *node)
{
int rc;
u32 ref_cnt_freq;
virtual_addr_t ref_cnt_addr;
u32 cpu = vmm_smp_processor_id();
struct twd_clockchip *cc = &this_cpu(twd_cc);
if (!twd_base) {
rc = vmm_devtree_regmap(node, &twd_base, 0);
if (rc) {
goto fail;
}
}
if (!twd_ppi_irq) {
rc = vmm_devtree_irq_get(node, &twd_ppi_irq, 0);
if (rc) {
goto fail_regunmap;
}
}
if (!twd_freq_hz) {
/* First try to find TWD clock */
if (!twd_clk) {
twd_clk = of_clk_get(node, 0);
}
if (!twd_clk) {
twd_clk = clk_get_sys("smp_twd", NULL);
}
if (twd_clk) {
/* Use TWD clock to find frequency */
rc = clk_prepare_enable(twd_clk);
if (rc) {
clk_put(twd_clk);
goto fail_regunmap;
}
twd_freq_hz = clk_get_rate(twd_clk);
} else {
/* No TWD clock found hence caliberate */
rc = vmm_devtree_regmap(node, &ref_cnt_addr, 1);
if (rc) {
vmm_devtree_regunmap(node, ref_cnt_addr, 1);
goto fail_regunmap;
}
if (vmm_devtree_read_u32(node, "ref-counter-freq",
&ref_cnt_freq)) {
vmm_devtree_regunmap(node, ref_cnt_addr, 1);
goto fail_regunmap;
}
twd_caliberate_freq(twd_base,
ref_cnt_addr, ref_cnt_freq);
vmm_devtree_regunmap(node, ref_cnt_addr, 1);
}
}
memset(cc, 0, sizeof(struct twd_clockchip));
vmm_sprintf(cc->name, "twd/%d", cpu);
cc->clkchip.name = cc->name;
cc->clkchip.hirq = twd_ppi_irq;
cc->clkchip.rating = 350;
cc->clkchip.cpumask = vmm_cpumask_of(cpu);
cc->clkchip.features =
VMM_CLOCKCHIP_FEAT_PERIODIC | VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&cc->clkchip.mult, &cc->clkchip.shift,
VMM_NSEC_PER_SEC, twd_freq_hz, 10);
cc->clkchip.min_delta_ns = vmm_clockchip_delta2ns(0xF, &cc->clkchip);
cc->clkchip.max_delta_ns =
vmm_clockchip_delta2ns(0xFFFFFFFF, &cc->clkchip);
cc->clkchip.set_mode = &twd_clockchip_set_mode;
cc->clkchip.set_next_event = &twd_clockchip_set_next_event;
cc->clkchip.priv = cc;
if (vmm_smp_is_bootcpu()) {
/* Register interrupt handler */
if ((rc = vmm_host_irq_register(twd_ppi_irq, "twd",
&twd_clockchip_irq_handler,
cc))) {
goto fail_regunmap;
}
/* Mark interrupt as per-cpu */
if ((rc = vmm_host_irq_mark_per_cpu(twd_ppi_irq))) {
goto fail_unreg_irq;
}
}
/* Explicitly enable local timer PPI in GIC
* Note: Local timer requires PPI support hence requires GIC
*/
gic_enable_ppi(twd_ppi_irq);
rc = vmm_clockchip_register(&cc->clkchip);
if (rc) {
goto fail_unreg_irq;
}
return VMM_OK;
fail_unreg_irq:
if (vmm_smp_is_bootcpu()) {
vmm_host_irq_unregister(twd_ppi_irq, cc);
}
fail_regunmap:
vmm_devtree_regunmap(node, twd_base, 0);
fail:
return rc;
}
static int __cpuinit generic_timer_clockchip_init(struct vmm_devtree_node *node)
{
int rc;
u32 irq[4], num_irqs, val;
struct vmm_clockchip *cc;
/* Get and Check generic timer frequency */
generic_timer_get_freq(node);
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
/* Get hypervisor timer irq number */
irq[GENERIC_HYPERVISOR_TIMER] = vmm_devtree_irq_parse_map(node,
GENERIC_HYPERVISOR_TIMER);
if (!irq[GENERIC_HYPERVISOR_TIMER]) {
return VMM_ENODEV;
}
/* Get physical timer irq number */
irq[GENERIC_PHYSICAL_TIMER] = vmm_devtree_irq_parse_map(node,
GENERIC_PHYSICAL_TIMER);
if (!irq[GENERIC_PHYSICAL_TIMER]) {
return VMM_ENODEV;
}
/* Get virtual timer irq number */
irq[GENERIC_VIRTUAL_TIMER] = vmm_devtree_irq_parse_map(node,
GENERIC_VIRTUAL_TIMER);
if (!irq[GENERIC_VIRTUAL_TIMER]) {
return VMM_ENODEV;
}
/* Number of generic timer irqs */
num_irqs = vmm_devtree_irq_count(node);
if (!num_irqs) {
return VMM_EFAIL;
}
/* Ensure hypervisor timer is stopped */
generic_timer_stop();
/* Create generic hypervisor timer clockchip */
cc = vmm_zalloc(sizeof(struct vmm_clockchip));
if (!cc) {
return VMM_EFAIL;
}
cc->name = "gen-hyp-timer";
cc->hirq = irq[GENERIC_HYPERVISOR_TIMER];
cc->rating = 400;
cc->cpumask = vmm_cpumask_of(vmm_smp_processor_id());
cc->features = VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&cc->mult, &cc->shift,
VMM_NSEC_PER_SEC, generic_timer_hz, 10);
cc->min_delta_ns = vmm_clockchip_delta2ns(0xF, cc);
cc->max_delta_ns = vmm_clockchip_delta2ns(0x7FFFFFFF, cc);
cc->set_mode = &generic_timer_set_mode;
cc->set_next_event = &generic_timer_set_next_event;
cc->priv = NULL;
/* Register hypervisor timer clockchip */
rc = vmm_clockchip_register(cc);
if (rc) {
goto fail_free_cc;
}
/* Register irq handler for hypervisor timer */
rc = vmm_host_irq_register(irq[GENERIC_HYPERVISOR_TIMER],
"gen-hyp-timer",
&generic_hyp_timer_handler, cc);
if (rc) {
goto fail_unreg_cc;
}
if (num_irqs > 1) {
/* Register irq handler for physical timer */
rc = vmm_host_irq_register(irq[GENERIC_PHYSICAL_TIMER],
"gen-phys-timer",
&generic_phys_timer_handler,
NULL);
if (rc) {
goto fail_unreg_htimer;
}
}
if (num_irqs > 2) {
/* Register irq handler for virtual timer */
rc = vmm_host_irq_register(irq[GENERIC_VIRTUAL_TIMER],
"gen-virt-timer",
&generic_virt_timer_handler,
NULL);
if (rc) {
goto fail_unreg_ptimer;
}
}
if (num_irqs > 1) {
val = generic_timer_reg_read(GENERIC_TIMER_REG_HCTL);
val |= GENERIC_TIMER_HCTL_KERN_PCNT_EN;
val |= GENERIC_TIMER_HCTL_KERN_PTMR_EN;
generic_timer_reg_write(GENERIC_TIMER_REG_HCTL, val);
}
return VMM_OK;
fail_unreg_ptimer:
if (num_irqs > 1) {
vmm_host_irq_unregister(irq[GENERIC_PHYSICAL_TIMER],
&generic_phys_timer_handler);
}
fail_unreg_htimer:
vmm_host_irq_unregister(irq[GENERIC_HYPERVISOR_TIMER],
&generic_hyp_timer_handler);
fail_unreg_cc:
vmm_clockchip_unregister(cc);
fail_free_cc:
vmm_free(cc);
return rc;
}
static int __cpuinit bcm2835_clockchip_init(struct vmm_devtree_node *node)
{
int rc;
u32 clock, hirq;
struct bcm2835_clockchip *bcc;
/* Read clock frequency */
rc = vmm_devtree_clock_frequency(node, &clock);
if (rc) {
return rc;
}
/* Read irq attribute */
rc = vmm_devtree_irq_get(node, &hirq, DEFAULT_TIMER);
if (rc) {
return rc;
}
bcc = vmm_zalloc(sizeof(struct bcm2835_clockchip));
if (!bcc) {
return VMM_ENOMEM;
}
/* Map timer registers */
rc = vmm_devtree_regmap(node, &bcc->base, 0);
if (rc) {
vmm_free(bcc);
return rc;
}
bcc->system_clock = (void *)(bcc->base + REG_COUNTER_LO);
bcc->control = (void *)(bcc->base + REG_CONTROL);
bcc->compare = (void *)(bcc->base + REG_COMPARE(DEFAULT_TIMER));
bcc->match_mask = 1 << DEFAULT_TIMER;
/* Setup clockchip */
bcc->clkchip.name = "bcm2835-clkchip";
bcc->clkchip.hirq = hirq;
bcc->clkchip.rating = 300;
bcc->clkchip.cpumask = vmm_cpumask_of(0);
bcc->clkchip.features = VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&bcc->clkchip.mult,
&bcc->clkchip.shift,
VMM_NSEC_PER_SEC, clock, 10);
bcc->clkchip.min_delta_ns = vmm_clockchip_delta2ns(MIN_REG_COMPARE,
&bcc->clkchip);
bcc->clkchip.max_delta_ns = vmm_clockchip_delta2ns(MAX_REG_COMPARE,
&bcc->clkchip);
bcc->clkchip.set_mode = &bcm2835_clockchip_set_mode;
bcc->clkchip.set_next_event = &bcm2835_clockchip_set_next_event;
bcc->clkchip.priv = bcc;
/* Make sure compare register is set to zero */
vmm_writel(0x0, bcc->compare);
/* Make sure pending timer interrupts acknowledged */
if (vmm_readl(bcc->control) & bcc->match_mask) {
vmm_writel(bcc->match_mask, bcc->control);
}
/* Register interrupt handler */
rc = vmm_host_irq_register(hirq, "bcm2835_timer",
&bcm2835_clockchip_irq_handler, bcc);
if (rc) {
vmm_devtree_regunmap(node, bcc->base, 0);
vmm_free(bcc);
return rc;
}
/* Register clockchip */
rc = vmm_clockchip_register(&bcc->clkchip);
if (rc) {
vmm_host_irq_unregister(hirq, bcc);
vmm_devtree_regunmap(node, bcc->base, 0);
vmm_free(bcc);
return rc;
}
return VMM_OK;
}
int __cpuinit generic_timer_clockchip_init(void)
{
int rc;
u32 irq[3], num_irqs, val;
struct vmm_clockchip *cc;
struct vmm_devtree_node *node;
/* Find generic timer device tree node */
node = vmm_devtree_find_matching(NULL, generic_timer_match);
if (!node) {
return VMM_ENODEV;
}
/* Determine generic timer frequency */
if (generic_timer_hz == 0) {
rc = vmm_devtree_clock_frequency(node, &generic_timer_hz);
if (rc) {
/* Use preconfigured counter frequency
* in absence of dts node
*/
generic_timer_hz =
generic_timer_reg_read(GENERIC_TIMER_REG_FREQ);
} else if (generic_timer_freq_writeable()) {
/* Program the counter frequency as per the dts node */
generic_timer_reg_write(GENERIC_TIMER_REG_FREQ,
generic_timer_hz);
}
}
if (generic_timer_hz == 0) {
return VMM_EFAIL;
}
/* Get hypervisor timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_HYPERVISOR_TIMER],
GENERIC_HYPERVISOR_TIMER);
if (rc) {
return rc;
}
/* Get physical timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_PHYSICAL_TIMER],
GENERIC_PHYSICAL_TIMER);
if (rc) {
return rc;
}
/* Get virtual timer irq number */
rc = vmm_devtree_irq_get(node,
&irq[GENERIC_VIRTUAL_TIMER],
GENERIC_VIRTUAL_TIMER);
if (rc) {
return rc;
}
/* Number of generic timer irqs */
num_irqs = vmm_devtree_irq_count(node);
if (!num_irqs) {
return VMM_EFAIL;
}
/* Ensure hypervisor timer is stopped */
generic_timer_stop();
/* Create generic hypervisor timer clockchip */
cc = vmm_zalloc(sizeof(struct vmm_clockchip));
if (!cc) {
return VMM_EFAIL;
}
cc->name = "gen-hyp-timer";
cc->hirq = irq[GENERIC_HYPERVISOR_TIMER];
cc->rating = 400;
cc->cpumask = vmm_cpumask_of(vmm_smp_processor_id());
cc->features = VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&cc->mult, &cc->shift,
VMM_NSEC_PER_SEC, generic_timer_hz, 10);
cc->min_delta_ns = vmm_clockchip_delta2ns(0xF, cc);
cc->max_delta_ns = vmm_clockchip_delta2ns(0x7FFFFFFF, cc);
cc->set_mode = &generic_timer_set_mode;
cc->set_next_event = &generic_timer_set_next_event;
cc->priv = NULL;
/* Register hypervisor timer clockchip */
rc = vmm_clockchip_register(cc);
if (rc) {
goto fail_free_cc;
}
if (!vmm_smp_processor_id()) {
/* Register irq handler for hypervisor timer */
rc = vmm_host_irq_register(irq[GENERIC_HYPERVISOR_TIMER],
"gen-hyp-timer",
&generic_hyp_timer_handler, cc);
if (rc) {
goto fail_unreg_cc;
}
/* Mark hypervisor timer irq as per-CPU */
if ((rc = vmm_host_irq_mark_per_cpu(cc->hirq))) {
goto fail_unreg_htimer;
}
if (num_irqs > 1) {
/* Register irq handler for physical timer */
rc = vmm_host_irq_register(irq[GENERIC_PHYSICAL_TIMER],
"gen-phys-timer",
&generic_phys_timer_handler,
NULL);
if (rc) {
goto fail_unreg_htimer;
}
/* Mark physical timer irq as per-CPU */
rc = vmm_host_irq_mark_per_cpu(
irq[GENERIC_PHYSICAL_TIMER]);
if (rc) {
goto fail_unreg_ptimer;
}
}
if (num_irqs > 2) {
/* Register irq handler for virtual timer */
rc = vmm_host_irq_register(irq[GENERIC_VIRTUAL_TIMER],
"gen-virt-timer",
&generic_virt_timer_handler,
NULL);
if (rc) {
goto fail_unreg_ptimer;
}
/* Mark virtual timer irq as per-CPU */
rc = vmm_host_irq_mark_per_cpu(
irq[GENERIC_VIRTUAL_TIMER]);
if (rc) {
goto fail_unreg_vtimer;
}
}
}
if (num_irqs > 1) {
val = generic_timer_reg_read(GENERIC_TIMER_REG_HCTL);
val |= GENERIC_TIMER_HCTL_KERN_PCNT_EN;
val |= GENERIC_TIMER_HCTL_KERN_PTMR_EN;
generic_timer_reg_write(GENERIC_TIMER_REG_HCTL, val);
}
for (val = 0; val < num_irqs; val++) {
gic_enable_ppi(irq[val]);
}
return VMM_OK;
fail_unreg_vtimer:
if (!vmm_smp_processor_id() && num_irqs > 2) {
vmm_host_irq_unregister(irq[GENERIC_HYPERVISOR_TIMER],
&generic_virt_timer_handler);
}
fail_unreg_ptimer:
if (!vmm_smp_processor_id() && num_irqs > 1) {
vmm_host_irq_unregister(irq[GENERIC_PHYSICAL_TIMER],
&generic_phys_timer_handler);
}
fail_unreg_htimer:
if (!vmm_smp_processor_id()) {
vmm_host_irq_unregister(irq[GENERIC_HYPERVISOR_TIMER],
&generic_hyp_timer_handler);
}
fail_unreg_cc:
vmm_clockchip_register(cc);
fail_free_cc:
vmm_free(cc);
return rc;
}
int __cpuinit epit_clockchip_init(void)
{
int rc = VMM_ENODEV;
u32 clock, hirq, timer_num, *val;
struct vmm_devtree_node *node;
struct epit_clockchip *ecc;
/* find the first epit compatible node */
node = vmm_devtree_find_compatible(NULL, NULL, "freescale,epit-timer");
if (!node) {
goto fail;
}
/* Read clock frequency */
rc = vmm_devtree_clock_frequency(node, &clock);
if (rc) {
goto fail;
}
/* Read timer_num attribute */
val = vmm_devtree_attrval(node, "timer_num");
if (!val) {
rc = VMM_ENOTAVAIL;
goto fail;
}
timer_num = *val;
/* Read irq attribute */
rc = vmm_devtree_irq_get(node, &hirq, 0);
if (rc) {
goto fail;
}
/* allocate our struct */
ecc = vmm_zalloc(sizeof(struct epit_clockchip));
if (!ecc) {
rc = VMM_ENOMEM;
goto fail;
}
/* Map timer registers */
rc = vmm_devtree_regmap(node, &ecc->base, 0);
if (rc) {
goto regmap_fail;
}
ecc->match_mask = 1 << timer_num;
ecc->timer_num = timer_num;
/* Setup clockchip */
ecc->clkchip.name = node->name;
ecc->clkchip.hirq = hirq;
ecc->clkchip.rating = 300;
ecc->clkchip.cpumask = vmm_cpumask_of(0);
ecc->clkchip.features = VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&ecc->clkchip.mult,
&ecc->clkchip.shift,
VMM_NSEC_PER_SEC, clock, 10);
ecc->clkchip.min_delta_ns = vmm_clockchip_delta2ns(MIN_REG_COMPARE,
&ecc->clkchip);
ecc->clkchip.max_delta_ns = vmm_clockchip_delta2ns(MAX_REG_COMPARE,
&ecc->clkchip);
ecc->clkchip.set_mode = epit_set_mode;
ecc->clkchip.set_next_event = epit_set_next_event;
ecc->clkchip.priv = ecc;
/*
* Initialise to a known state (all timers off, and timing reset)
*/
vmm_writel(0x0, (void *)(ecc->base + EPITCR));
/*
* Initialize the load register to the max value to decrement.
*/
vmm_writel(0xffffffff, (void *)(ecc->base + EPITLR));
/*
* enable the timer, set it to the high reference clock,
* allow the timer to work in WAIT mode.
*/
vmm_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
(void *)(ecc->base + EPITCR));
/* Register interrupt handler */
rc = vmm_host_irq_register(hirq, ecc->clkchip.name,
&epit_timer_interrupt, ecc);
if (rc) {
goto irq_fail;
}
/* Register clockchip */
rc = vmm_clockchip_register(&ecc->clkchip);
if (rc) {
goto register_fail;
}
return VMM_OK;
register_fail:
vmm_host_irq_unregister(hirq, ecc);
irq_fail:
vmm_devtree_regunmap(node, ecc->base, 0);
regmap_fail:
vmm_free(ecc);
fail:
return rc;
}
int __cpuinit twd_clockchip_init(virtual_addr_t ref_counter_addr,
u32 ref_counter_freq)
{
int rc;
u32 cpu = vmm_smp_processor_id();
struct vmm_devtree_node *node;
struct twd_clockchip *cc = &this_cpu(twd_cc);
node = vmm_devtree_find_matching(NULL, twd_match);
if (!node) {
return VMM_ENODEV;
}
if (!twd_base) {
rc = vmm_devtree_regmap(node, &twd_base, 0);
if (rc) {
return rc;
}
}
if (!twd_ppi_irq) {
rc = vmm_devtree_irq_get(node, &twd_ppi_irq, 0);
if (rc) {
return rc;
}
}
twd_caliberate_freq(twd_base, ref_counter_addr, ref_counter_freq);
memset(cc, 0, sizeof(struct twd_clockchip));
vmm_sprintf(cc->name, "twd/%d", cpu);
cc->clkchip.name = cc->name;
cc->clkchip.hirq = twd_ppi_irq;
cc->clkchip.rating = 350;
cc->clkchip.cpumask = vmm_cpumask_of(cpu);
cc->clkchip.features =
VMM_CLOCKCHIP_FEAT_PERIODIC | VMM_CLOCKCHIP_FEAT_ONESHOT;
vmm_clocks_calc_mult_shift(&cc->clkchip.mult, &cc->clkchip.shift,
VMM_NSEC_PER_SEC, twd_freq_hz, 10);
cc->clkchip.min_delta_ns = vmm_clockchip_delta2ns(0xF, &cc->clkchip);
cc->clkchip.max_delta_ns =
vmm_clockchip_delta2ns(0xFFFFFFFF, &cc->clkchip);
cc->clkchip.set_mode = &twd_clockchip_set_mode;
cc->clkchip.set_next_event = &twd_clockchip_set_next_event;
cc->clkchip.priv = cc;
if (!cpu) {
/* Register interrupt handler */
if ((rc = vmm_host_irq_register(twd_ppi_irq, "twd",
&twd_clockchip_irq_handler,
cc))) {
return rc;
}
/* Mark interrupt as per-cpu */
if ((rc = vmm_host_irq_mark_per_cpu(twd_ppi_irq))) {
return rc;
}
}
/* Explicitly enable local timer PPI in GIC
* Note: Local timer requires PPI support hence requires GIC
*/
gic_enable_ppi(twd_ppi_irq);
return vmm_clockchip_register(&cc->clkchip);
}
