VOID displayCursorVMWareSVGA(struct HWData *data, LONG mode)
{
#if 0
writeVMWareSVGAFIFO(data, SVGA_CMD_DISPLAY_CURSOR);
writeVMWareSVGAFIFO(data, 1);
writeVMWareSVGAFIFO(data, mode);
syncVMWareSVGAFIFO(data);
#else
vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
vmwareWriteReg(data, SVGA_REG_CURSOR_ON, mode);
#endif
}
VOID moveCursorVMWareSVGA(struct HWData *data, LONG x, LONG y)
{
#if 0
writeVMWareSVGAFIFO(data, SVGA_CMD_MOVE_CURSOR);
writeVMWareSVGAFIFO(data, x);
writeVMWareSVGAFIFO(data, y);
syncVMWareSVGAFIFO(data);
#else
vmwareWriteReg(data, SVGA_REG_CURSOR_ID, 1);
vmwareWriteReg(data, SVGA_REG_CURSOR_X, x);
vmwareWriteReg(data, SVGA_REG_CURSOR_Y, y);
vmwareWriteReg(data, SVGA_REG_CURSOR_ON, 1);
#endif
}
VMware::~VMware()
{
vmwareWriteReg(SVGA_REG_CONFIG_DONE, 0);
vmwareWriteReg(SVGA_REG_ENABLE, 0);
if(m_hFifoArea != -1)
{
delete_area(m_hFifoArea);
}
if(m_hFbArea != -1)
{
delete_area(m_hFbArea);
}
}
ULONG getVMWareSVGAID(struct HWData *data)
{
ULONG id;
vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_2);
id = vmwareReadReg(data, SVGA_REG_ID);
if (id == SVGA_ID_2)
return id;
vmwareWriteReg(data, SVGA_REG_ID, SVGA_ID_1);
id = vmwareReadReg(data, SVGA_REG_ID);
if (id == SVGA_ID_1)
return id;
if (id == SVGA_ID_0)
return id;
return SVGA_ID_INVALID;
}
BOOL initVMWareSVGAHW(struct HWData *data, OOP_Object *device)
{
ULONG *ba;
ULONG id;
id = getVMWareSVGAID(data);
if ((id == SVGA_ID_0) || (id == SVGA_ID_INVALID))
{
return FALSE;
}
initVMWareSVGAFIFO(data);
data->capabilities = vmwareReadReg(data, SVGA_REG_CAPABILITIES);
if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
{
data->bitsperpixel = vmwareReadReg(data, SVGA_REG_HOST_BITS_PER_PIXEL);
vmwareWriteReg(data,SVGA_REG_BITS_PER_PIXEL, data->bitsperpixel);
}
data->bitsperpixel = vmwareReadReg(data, SVGA_REG_BITS_PER_PIXEL);
data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
data->maxwidth = vmwareReadReg(data, SVGA_REG_MAX_WIDTH);
data->maxheight = vmwareReadReg(data, SVGA_REG_MAX_HEIGHT);
data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
data->bytesperpixel = 1;
if (data->depth>16)
data->bytesperpixel = 4;
else if (data->depth>8)
data->bytesperpixel = 2;
if (data->capabilities & SVGA_CAP_MULTIMON)
{
data->displaycount = vmwareReadReg(data, SVGA_REG_NUM_DISPLAYS);
}
else
{
data->displaycount = 1;
}
data->vramsize = vmwareReadReg(data, SVGA_REG_VRAM_SIZE);
data->vrambase = vmwareReadReg(data, SVGA_REG_FB_START);
data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
D(bug("[VMWareSVGA] Init: VRAM at 0x%08x size %d\n",data->vrambase, data->vramsize));
D(bug("[VMWareSVGA] Init: no.displays: %d\n",data->displaycount));
D(bug("[VMWareSVGA] Init: caps : 0x%08x\n",data->capabilities));
D(bug("[VMWareSVGA] Init: no.displays: %d\n",data->displaycount));
D(bug("[VMWareSVGA] Init: depth: %d\n",data->depth));
D(bug("[VMWareSVGA] Init: bpp : %d\n",data->bitsperpixel));
D(bug("[VMWareSVGA] Init: maxw: %d\n",data->maxwidth));
D(bug("[VMWareSVGA] Init: maxh: %d\n",data->maxheight));
return TRUE;
}
void
vmwareWriteCursorRegs(VMWAREPtr pVMWARE, Bool visible, Bool force)
{
int enableVal;
vmwareWriteReg(pVMWARE, SVGA_REG_CURSOR_ID, MOUSE_ID);
if (visible) {
vmwareWriteReg(pVMWARE, SVGA_REG_CURSOR_X, pVMWARE->hwcur.x);
vmwareWriteReg(pVMWARE, SVGA_REG_CURSOR_Y, pVMWARE->hwcur.y);
}
if (force) {
enableVal = visible ? SVGA_CURSOR_ON_SHOW : SVGA_CURSOR_ON_HIDE;
} else {
enableVal = visible ? pVMWARE->cursorRestoreToFB :
pVMWARE->cursorRemoveFromFB;
}
vmwareWriteReg(pVMWARE, SVGA_REG_CURSOR_ON, enableVal);
}
VOID setModeVMWareSVGA(struct HWData *data, ULONG width, ULONG height)
{
D(bug("[VMWareSVGA] SetMode: %dx%d\n",width,height));
vmwareWriteReg(data, SVGA_REG_ENABLE, 0);
vmwareWriteReg(data, SVGA_REG_WIDTH, width);
vmwareWriteReg(data, SVGA_REG_HEIGHT, height);
if (data->capabilities & SVGA_CAP_8BIT_EMULATION)
vmwareWriteReg(data, SVGA_REG_BITS_PER_PIXEL,data->bitsperpixel);
vmwareWriteReg(data, SVGA_REG_ENABLE, 1);
data->fboffset = vmwareReadReg(data, SVGA_REG_FB_OFFSET);
data->bytesperline = vmwareReadReg(data, SVGA_REG_BYTES_PER_LINE);
data->depth = vmwareReadReg(data, SVGA_REG_DEPTH);
data->redmask = vmwareReadReg(data, SVGA_REG_RED_MASK);
data->greenmask = vmwareReadReg(data, SVGA_REG_GREEN_MASK);
data->bluemask = vmwareReadReg(data, SVGA_REG_BLUE_MASK);
data->pseudocolor = vmwareReadReg(data, SVGA_REG_PSEUDOCOLOR);
}
/*
*-----------------------------------------------------------------------------
*
* VMXGetVMwareSvgaId --
*
* Retrieve the SVGA_ID of the VMware SVGA adapter.
* This function should hide any backward compatibility mess.
*
* Results:
* The SVGA_ID_* of the present VMware adapter.
*
* Side effects:
* ins/outs
*
*-----------------------------------------------------------------------------
*/
uint32
VMXGetVMwareSvgaId(uint16 indexReg, uint16 valueReg)
{
uint32 vmware_svga_id;
/* Any version with any SVGA_ID_* support will initialize SVGA_REG_ID
* to SVGA_ID_0 to support versions of this driver with SVGA_ID_0.
*
* Versions of SVGA_ID_0 ignore writes to the SVGA_REG_ID register.
*
* Versions of SVGA_ID_1 will allow us to overwrite the content
* of the SVGA_REG_ID register only with the values SVGA_ID_0 or SVGA_ID_1.
*
* Versions of SVGA_ID_2 will allow us to overwrite the content
* of the SVGA_REG_ID register only with the values SVGA_ID_0 or SVGA_ID_1
* or SVGA_ID_2.
*/
vmwareWriteReg (indexReg, valueReg, SVGA_REG_ID, SVGA_ID_2);
vmware_svga_id = vmwareReadReg (indexReg, valueReg, SVGA_REG_ID);
IOLog ("VMwareFB: read ID: (0x%08x)\n", vmware_svga_id);
if (vmware_svga_id == SVGA_ID_2) {
return SVGA_ID_2;
}
vmwareWriteReg (indexReg, valueReg, SVGA_REG_ID, SVGA_ID_1);
vmware_svga_id = vmwareReadReg (indexReg, valueReg, SVGA_REG_ID);
IOLog ("VMwareFB: read ID: (0x%08x)\n", vmware_svga_id);
if (vmware_svga_id == SVGA_ID_1) {
return SVGA_ID_1;
}
if (vmware_svga_id == SVGA_ID_0) {
return SVGA_ID_0;
}
/* No supported VMware SVGA devices found */
return SVGA_ID_INVALID;
}
/* Returns the highest SVGA Id supported by the video card */
uint32 VMware::vmwareGetSvgaId(void)
{
uint32 svgaId;
vmwareWriteReg(SVGA_REG_ID, SVGA_ID_2);
svgaId = vmwareReadReg(SVGA_REG_ID);
if(svgaId == (uint32)SVGA_ID_2)
return SVGA_ID_2;
vmwareWriteReg(SVGA_REG_ID, SVGA_ID_1);
svgaId = vmwareReadReg(SVGA_REG_ID);
if(svgaId == (uint32)SVGA_ID_1)
return SVGA_ID_1;
vmwareWriteReg(SVGA_REG_ID, SVGA_ID_0);
svgaId = vmwareReadReg(SVGA_REG_ID);
if(svgaId == (uint32)SVGA_ID_0)
return SVGA_ID_0;
/* No supported VMware SVGA devices found */
return SVGA_ID_INVALID;
}
VOID initVMWareSVGAFIFO(struct HWData *data)
{
ULONG *fifo;
ULONG fifomin;
vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 0); //Stop vmware from reading the fifo
fifo = data->mmiobase = vmwareReadReg(data, SVGA_REG_MEM_START);
data->mmiosize = vmwareReadReg(data, SVGA_REG_MEM_SIZE) & ~3;
if (data->capabilities & SVGA_CAP_EXTENDED_FIFO)
fifomin = vmwareReadReg(data, SVGA_REG_MEM_REGS);
else
fifomin =4;
fifo[SVGA_FIFO_MIN] = fifomin * sizeof(ULONG);
/* reduce size of FIFO queue to prevent VMWare from failing */
fifo[SVGA_FIFO_MAX] = (data->mmiosize > 65536) ? 65536 : data->mmiosize;
fifo[SVGA_FIFO_NEXT_CMD] = fifomin * sizeof(ULONG);
fifo[SVGA_FIFO_STOP] = fifomin * sizeof(ULONG);
vmwareWriteReg(data, SVGA_REG_CONFIG_DONE, 1);
}
void
vmwareWriteWordToFIFO (CARD32* vmwareFIFO, uint16 indexReg, uint16 valueReg, CARD32 value)
{
/* Need to sync? */
if ((vmwareFIFO[SVGA_FIFO_NEXT_CMD] + sizeof (CARD32) == vmwareFIFO[SVGA_FIFO_STOP])
|| (vmwareFIFO[SVGA_FIFO_NEXT_CMD] == vmwareFIFO[SVGA_FIFO_MAX] - sizeof(CARD32) &&
vmwareFIFO[SVGA_FIFO_STOP] == vmwareFIFO[SVGA_FIFO_MIN])) {
vmwareWriteReg(indexReg, valueReg, SVGA_REG_SYNC, 1);
while (vmwareReadReg(indexReg, valueReg, SVGA_REG_BUSY))
; // nothing
}
vmwareFIFO[vmwareFIFO[SVGA_FIFO_NEXT_CMD] / sizeof (CARD32)] = value;
vmwareFIFO[SVGA_FIFO_NEXT_CMD] += sizeof (CARD32);
if (vmwareFIFO[SVGA_FIFO_NEXT_CMD] == vmwareFIFO[SVGA_FIFO_MAX]) {
vmwareFIFO[SVGA_FIFO_NEXT_CMD] = vmwareFIFO[SVGA_FIFO_MIN];
}
}
VOID syncVMWareSVGAFIFO(struct HWData *data)
{
vmwareWriteReg(data, SVGA_REG_SYNC, 1);
while (vmwareReadReg(data, SVGA_REG_BUSY) != 0);
#warning "maybe wait (delay) some time"
}
VMware::VMware()
: m_cGELock("VMware_ge_lock")
{
int pciItor, chipItor;
bool vidCardFound = false;
/* Give safe values to all the class data members */
InitMembers();
for(pciItor = 0; get_pci_info(&m_cPciInfo, pciItor) == 0; pciItor++)
{
m_vmChipInfo.nChipId = (m_cPciInfo.nVendorID << 16) | (m_cPciInfo.nDeviceID);
for(chipItor = 0; chipItor < numSupportedChips; chipItor++)
{
if(m_vmChipInfo.nChipId == supportedChips[chipItor].nChipId)
{
vidCardFound = true;
m_vmChipInfo.nArchRev = supportedChips[chipItor].nArchRev;
m_vmChipInfo.pzName = supportedChips[chipItor].pzName;
break;
}
}
if(vidCardFound)
break;
}
if(!vidCardFound)
{
printf("VMware - Did not find any VMware video cards.\n");
return;
}
dbprintf("VMware - Found match - PCI %d: Vendor 0x%04x "
"Device 0x%04x - Rev 0x%04x\n", pciItor,
m_cPciInfo.nVendorID, m_cPciInfo.nDeviceID,
m_cPciInfo.nRevisionID);
/* Initialize the hardware. This will setup the
* IO ports and write to m_regId */
if(!InitHardware())
{
dbprintf("VMware - Unable to initialize hardware.\n");
vmwareWriteReg(SVGA_REG_CONFIG_DONE, 0);
vmwareWriteReg(SVGA_REG_ENABLE, 0);
return;
}
dbprintf("VMware - Host bpp is %d\n", (int) m_regHostBPP);
dbprintf("VMware - Current Guest bpp is set to %d\n", (int) m_regBitsPerPixel);
dbprintf("VMware - Only allowing %d bpp\n", (int) m_regBitsPerPixel);
int bpp;
color_space colspace;
float rf[] = {60.0f};
if(m_regBitsPerPixel == 16)
{
bpp = 2;
colspace = CS_RGB16;
}
else if(m_regBitsPerPixel == 32)
{
bpp = 4;
colspace = CS_RGB32;
}
else
{
dbprintf("VMware - m_regBitsPerPixel is unexpected value of %d\n",
(int) m_regBitsPerPixel);
return;
}
for(int j = 0; j < 4; j++)
{
m_cScreenModeList.push_back(os::screen_mode(640, 480, 640 * bpp, colspace, rf[j]));
m_cScreenModeList.push_back(os::screen_mode(800, 600, 800 * bpp, colspace, rf[j]));
m_cScreenModeList.push_back(os::screen_mode(1024, 768, 1024 * bpp, colspace, rf[j]));
}
m_bIsInitiated = true;
return;
}
/* Returns true/false if initialization was successful */
bool VMware::InitHardware(void)
{
/* This has to be done first, otherwise we can't
* access the SVGA registers */
if(!setupIoPorts())
{
dbprintf("VMware - Failed to setup the IO ports.\n");
return false;
}
/*** Grab the SVGA Id ***/
m_regId = vmwareGetSvgaId();
if(m_regId == (uint32)SVGA_ID_2)
{
dbprintf("VMware - SVGA Id is SVGA_ID_2\n");
}
else if(m_regId == (uint32)SVGA_ID_1)
{
dbprintf("VMware - SVGA Id is SVGA_ID_1\n");
return false;
}
else if(m_regId == (uint32)SVGA_ID_0)
{
dbprintf("VMware - SVGA Id is SVGA_ID_0\n");
return false;
}
else
{
dbprintf("VMware - SVGA Id is SVGA_ID_INVALID\n");
return false;
}
/*** Map the frame buffer and the command FIFO ***/
if(!CreateFb())
{
dbprintf("VMware -Failed to map the frame buffer.\n");
return false;
}
dbprintf("VMware - Successfully mapped the frame buffer.\n");
if(!CreateFifo())
{
dbprintf("VMware - Failed to map the command FIFO.\n");
return false;
}
dbprintf("VMware - Successfully mapped the command FIFO.\n");
/*** Initialize the FB ***/
if(!InitFb())
{
dbprintf("VMware - Failed to initialized the frame buffer.\n");
return false;
}
dbprintf("VMware - Successfully initialized the frame buffer.\n");
/*** Initialize the command FIFO ***/
if(!InitFifo())
{
dbprintf("VMware - Failed to initialized the command FIFO.\n");
return false;
}
dbprintf("VMware - Successfully initialized the command FIFO.\n");
/*** Initially disable hardware cursor ***/
vmwareWriteReg(SVGA_REG_CURSOR_X, 0);
vmwareWriteReg(SVGA_REG_CURSOR_Y, 0);
vmwareWriteReg(SVGA_REG_CURSOR_ON, SVGA_CURSOR_ON_HIDE);
return true;
}
void VMware::Close()
{
vmwareWriteReg(SVGA_REG_CONFIG_DONE, 0);
vmwareWriteReg(SVGA_REG_ENABLE, 0);
}
