void
inject_guest_interruption(VCPU *vcpu, u64 vec)
{
u64 viva;
REGS *regs;
ISR pt_isr;
perfc_incra(vmx_inject_guest_interruption, vec >> 8);
regs = vcpu_regs(vcpu);
// clear cr.isr.ir (incomplete register frame)
pt_isr.val = VMX(vcpu,cr_isr);
pt_isr.ir = 0;
VMX(vcpu,cr_isr) = pt_isr.val;
collect_interruption(vcpu);
vmx_ia64_set_dcr(vcpu);
viva = vmx_vcpu_get_iva(vcpu);
regs->cr_iip = viva + vec;
debugger_event(vec == IA64_EXTINT_VECTOR ?
XEN_IA64_DEBUG_ON_EXTINT : XEN_IA64_DEBUG_ON_EXCEPT);
}
IA64FAULT vmx_vcpu_rfi(VCPU *vcpu)
{
// TODO: Only allowed for current vcpu
u64 ifs, psr;
REGS *regs = vcpu_regs(vcpu);
psr = VCPU(vcpu,ipsr);
if (psr & IA64_PSR_BN)
vcpu_bsw1(vcpu);
else
vcpu_bsw0(vcpu);
vmx_vcpu_set_psr(vcpu,psr);
vmx_ia64_set_dcr(vcpu);
ifs=VCPU(vcpu,ifs);
if(ifs>>63)
regs->cr_ifs = ifs;
regs->cr_iip = VCPU(vcpu,iip);
return (IA64_NO_FAULT);
}
void
vmx_load_all_rr(VCPU *vcpu)
{
unsigned long rr0, rr4;
switch (vcpu->arch.arch_vmx.mmu_mode) {
case VMX_MMU_VIRTUAL:
rr0 = vcpu->arch.metaphysical_saved_rr0;
rr4 = vcpu->arch.metaphysical_saved_rr4;
break;
case VMX_MMU_PHY_DT:
rr0 = vcpu->arch.metaphysical_rid_dt;
rr4 = vcpu->arch.metaphysical_rid_dt;
break;
case VMX_MMU_PHY_D:
rr0 = vcpu->arch.metaphysical_rid_d;
rr4 = vcpu->arch.metaphysical_rid_d;
break;
default:
panic_domain(NULL, "bad mmu mode value");
}
ia64_set_rr((VRN0 << VRN_SHIFT), rr0);
ia64_dv_serialize_data();
ia64_set_rr((VRN4 << VRN_SHIFT), rr4);
ia64_dv_serialize_data();
ia64_set_rr((VRN1 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN1])));
ia64_dv_serialize_data();
ia64_set_rr((VRN2 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN2])));
ia64_dv_serialize_data();
ia64_set_rr((VRN3 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN3])));
ia64_dv_serialize_data();
ia64_set_rr((VRN5 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN5])));
ia64_dv_serialize_data();
ia64_set_rr((VRN6 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN6])));
ia64_dv_serialize_data();
vmx_switch_rr7_vcpu(vcpu, vrrtomrr(vcpu, VMX(vcpu, vrr[VRN7])));
ia64_set_pta(VMX(vcpu, mpta));
vmx_ia64_set_dcr(vcpu);
ia64_srlz_d();
}
