// CHECK-LABEL: test_vqdmlslh_lane_s16 int32_t test_vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t c) { return vqdmlslh_lane_s16(a, b, c, 3); // CHECK: sqdmlsl {{s[0-9]+|v[0-9]+.4s}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3] }
// CHECK-LABEL: define i32 @test_vqdmlslh_lane_s16(i32 %a, i16 %b, <4 x i16> %c) #0 { // CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %c to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> // CHECK: [[LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 // CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0 // CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0 // CHECK: [[VQDMLXL:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP2]], <4 x i16> [[TMP3]]) // CHECK: [[LANE0:%.*]] = extractelement <4 x i32> [[VQDMLXL]], i64 0 // CHECK: [[VQDMLXL1:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %a, i32 [[LANE0]]) // CHECK: ret i32 [[VQDMLXL1]] int32_t test_vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t c) { return vqdmlslh_lane_s16(a, b, c, 3); }
int32x1_t test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c) { return vqdmlslh_lane_s16 (a, b, c, 3); }