/**
* w1_reset_bus() - Issues a reset bus sequence.
* @dev: the master device
* Return: 0=Device present, 1=No device present or error
*/
int w1_reset_bus(struct w1_master *dev)
{
int result;
unsigned long flags = 0;
if(w1_disable_irqs) local_irq_save(flags);
if (dev->bus_master->reset_bus)
result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
else {
dev->bus_master->write_bit(dev->bus_master->data, 0);
/* minimum 480, max ? us
* be nice and sleep, except 18b20 spec lists 960us maximum,
* so until we can sleep with microsecond accuracy, spin.
* Feel free to come up with some other way to give up the
* cpu for such a short amount of time AND get it back in
* the maximum amount of time.
*/
w1_delay(500);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(70);
result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
/* minimum 70 (above) + 430 = 500 us
* There aren't any timing requirements between a reset and
* the following transactions. Sleeping is safe here.
*/
/* w1_delay(430); min required time */
msleep(1);
}
if(w1_disable_irqs) local_irq_restore(flags);
return result;
}
/**
* Generates a write-1 cycle and samples the level.
* Only call if dev->bus_master->touch_bit is NULL
*/
static u8 w1_gpio_read_bit(void *data)
{
struct w1_gpio_msm_platform_data *pdata = data;
int result;
void (*write_bit)(void *, u8);
unsigned long irq_flags;
if (pdata->is_open_drain) {
write_bit = w1_gpio_write_bit_val;
} else {
write_bit = w1_gpio_write_bit_dir;
}
spin_lock_irqsave(&w1_gpio_msm_lock, irq_flags);
/* sample timing is critical here */
write_bit(data, 0);
write_bit(data, 1);
result = w1_gpio_read_bit_val(data);
(pdata->slave_speed == 0)? w1_delay(55) : w1_delay(8);
spin_unlock_irqrestore(&w1_gpio_msm_lock, irq_flags);
return result & 0x1;
}
int w1_reset_bus(struct w1_master *dev)
{
int result;
if (dev->bus_master->reset_bus)
result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
else {
dev->bus_master->write_bit(dev->bus_master->data, 0);
/*
*/
w1_delay(480);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(70);
result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
/*
*/
/* */
msleep(1);
}
return result;
}
/**
* Generates a write-0 or write-1 cycle.
* Only call if dev->bus_master->touch_bit is NULL
*/
static void w1_write_bit(struct w1_master *dev, int bit)
{
if (bit) {
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(6);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(64);
} else {
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(60);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(10);
}
}
/**
* Generates a write-1 cycle and samples the level.
* Only call if dev->bus_master->touch_bit is NULL
*/
static u8 w1_read_bit(struct w1_master *dev)
{
int result;
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(6);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(9);
result = dev->bus_master->read_bit(dev->bus_master->data);
w1_delay(55);
return result & 0x1;
}
/**
* Generates a write-0 or write-1 cycle.
* Only call if dev->bus_master->touch_bit is NULL
*/
static void w1_gpio_write_bit(void *data, u8 bit)
{
struct w1_gpio_msm_platform_data *pdata = data;
void (*write_bit)(void *, u8);
unsigned long irq_flags;
if (pdata->is_open_drain) {
write_bit = w1_gpio_write_bit_val;
} else {
write_bit = w1_gpio_write_bit_dir;
}
spin_lock_irqsave(&w1_gpio_msm_lock, irq_flags);
if (bit) {
write_bit(data, 0);
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(64) : w1_delay(10);
} else {
write_bit(data, 0);
#ifdef CONFIG_W1_SLAVE_DS28E15 /* delay time for DS28EL15 */
(pdata->slave_speed == 0)? w1_delay(60) : w1_delay(8);
#else /* delay time for DS28EL35 */
(pdata->slave_speed == 0)? w1_delay(60) : w1_delay(9);
#endif
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(10) : w1_delay(10);
}
spin_unlock_irqrestore(&w1_gpio_msm_lock, irq_flags);
}
/**
* Generates a write-0 or write-1 cycle.
* Only call if dev->bus_master->touch_bit is NULL
*/
static void w1_gpio_write_bit_in8(void *data, u8 bit)
{
struct w1_gpio_msm_platform_data *pdata = data;
void (*write_bit)(void *, u8);
if (pdata->is_open_drain) {
write_bit = w1_gpio_write_bit_val;
} else {
write_bit = w1_gpio_write_bit_dir;
}
if (bit) {
write_bit(data, 0);
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(64) : w1_delay(10);
} else {
write_bit(data, 0);
#ifdef CONFIG_W1_SLAVE_DS28E15 /* delay time for DS28EL15 */
(pdata->slave_speed == 0)? w1_delay(60) : w1_delay(8);
#else /* delay time for DS28EL35 */
(pdata->slave_speed == 0)? w1_delay(60) : w1_delay(9);
#endif
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(10) : w1_delay(10);
}
}
/**
* w1_read_bit() - Generates a write-1 cycle and samples the level.
* @dev: the master device
*
* Only call if dev->bus_master->touch_bit is NULL
*/
static u8 w1_read_bit(struct w1_master *dev)
{
int result;
unsigned long flags = 0;
/* sample timing is critical here */
local_irq_save(flags);
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(6);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(9);
result = dev->bus_master->read_bit(dev->bus_master->data);
local_irq_restore(flags);
w1_delay(55);
return result & 0x1;
}
/**
* w1_write_bit() - Generates a write-0 or write-1 cycle.
* @dev: the master device
* @bit: bit to write
*
* Only call if dev->bus_master->touch_bit is NULL
*/
static void w1_write_bit(struct w1_master *dev, int bit)
{
unsigned long flags = 0;
if(w1_disable_irqs) local_irq_save(flags);
if (bit) {
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(6);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(64);
} else {
dev->bus_master->write_bit(dev->bus_master->data, 0);
w1_delay(60);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(10);
}
if(w1_disable_irqs) local_irq_restore(flags);
}
/**
* Generates a write-0 or write-1 cycle.
* Only call if dev->bus_master->touch_bit is NULL
*/
static void w1_gpio_write_bit(void *data, u8 bit)
{
struct w1_gpio_msm_platform_data *pdata = data;
void (*write_bit)(void *, u8);
unsigned long irq_flags;
if (pdata->is_open_drain) {
write_bit = w1_gpio_write_bit_val;
} else {
write_bit = w1_gpio_write_bit_dir;
}
spin_lock_irqsave(&w1_gpio_msm_lock, irq_flags);
if (bit) {
write_bit(data, 0);
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(64) : w1_delay(10);
} else {
write_bit(data, 0);
(pdata->slave_speed == 0)? w1_delay(60) : w1_delay(8);
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(10) : w1_delay(5);
}
spin_unlock_irqrestore(&w1_gpio_msm_lock, irq_flags);
}
/**
* Issues a reset bus sequence.
*
* @param dev The bus master pointer
* @return 0=Device present, 1=No device present or error
*/
static u8 w1_gpio_reset_bus(void *data)
{
int result;
struct w1_gpio_msm_platform_data *pdata = data;
void (*write_bit)(void *, u8);
unsigned long irq_flags;
if (pdata->is_open_drain) {
write_bit = w1_gpio_write_bit_val;
} else {
write_bit = w1_gpio_write_bit_dir;
}
spin_lock_irqsave(&w1_gpio_msm_lock, irq_flags);
write_bit(data, 0);
/* minimum 480, max ? us
* be nice and sleep, except 18b20 spec lists 960us maximum,
* so until we can sleep with microsecond accuracy, spin.
* Feel free to come up with some other way to give up the
* cpu for such a short amount of time AND get it back in
* the maximum amount of time.
*/
(pdata->slave_speed == 0)? w1_delay(480) : w1_delay(48);
write_bit(data, 1);
(pdata->slave_speed == 0)? w1_delay(70) : w1_delay(7);
result = w1_gpio_read_bit_val(data) & 0x1;
/* minmum 70 (above) + 410 = 480 us
* There aren't any timing requirements between a reset and
* the following transactions. Sleeping is safe here.
*/
/* w1_delay(410); min required time */
(pdata->slave_speed == 0)? msleep(1) : w1_delay(40);
spin_unlock_irqrestore(&w1_gpio_msm_lock, irq_flags);
return result;
}
