/* * Routine: watchdog_init * Description: Shut down watch dogs */ void watchdog_init(void) { struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; writel(WD_UNLOCK1, &wd2_base->wspr); wait_for_command_complete(wd2_base); writel(WD_UNLOCK2, &wd2_base->wspr); }
/**************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************/ void watchdog_init(void) { /* There are 4 watch dogs. 1 secure, and 3 general purpose. * The ROM takes care of the secure one. Of the 3 GP ones, * 1 can reset us directly, the other 2 only generate MPU interrupts. */ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); wait_for_command_complete(WD2_BASE); __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); }
/**************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************/ void watchdog_init(void) { /* There are 4 watch dogs. 1 secure, and 3 general purpose. * The ROM takes care of the secure one. Of the 3 GP ones, * 1 can reset us directly, the other 2 only generate MPU interrupts. */ __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); wait_for_command_complete(WD2_BASE); __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); wait_for_command_complete(WD3_BASE); __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); wait_for_command_complete(WD4_BASE); __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); #endif }
/****************************************************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************************************************/ void watchdog_init(void) { /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is * either taken care of by ROM (HS/EMU) or not accessible (GP). * We need to take care of WD2-MPU or take a PRCM reset. WD3 * should not be running and does not generate a PRCM reset. */ sr32(CM_FCLKEN_WKUP, 5, 1, 1); sr32(CM_ICLKEN_WKUP, 5, 1, 1); wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); wait_for_command_complete(WD2_BASE); __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); }
/****************************************************************************** * Routine: watchdog_init * Description: Shut down watch dogs *****************************************************************************/ void watchdog_init(void) { watchdog_t *wd2_base = (watchdog_t *)WD2_BASE; prcm_t *prcm_base = (prcm_t *)PRCM_BASE; /* * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is * either taken care of by ROM (HS/EMU) or not accessible (GP). * We need to take care of WD2-MPU or take a PRCM reset. WD3 * should not be running and does not generate a PRCM reset. */ sr32(&prcm_base->fclken_wkup, 5, 1, 1); sr32(&prcm_base->iclken_wkup, 5, 1, 1); wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); writel(WD_UNLOCK1, &wd2_base->wspr); wait_for_command_complete(wd2_base); writel(WD_UNLOCK2, &wd2_base->wspr); }