int wasp_mem_config(void){ unsigned int reg32; wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL); /* Take WMAC out of reset */ reg32 = ar7240_reg_rd(AR7240_RESET); reg32 = reg32 & ~AR7240_RESET_WMAC; ar7240_reg_wr_nf(AR7240_RESET, reg32); /* Switching regulator settings */ ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */ ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */ //wasp_usb_initial_config(); gpio_config(); /* Needed here not to mess with Ethernet clocks */ ath_set_tuning_caps(); // return memory size return(ar7240_ddr_find_size()); }
int wasp_mem_config(void) { unsigned int type, reg32; type = wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL); /* Take WMAC out of reset */ reg32 = ar7240_reg_rd(AR7240_RESET); reg32 = reg32 & ~AR7240_RESET_WMAC; ar7240_reg_wr_nf(AR7240_RESET, reg32); /* Switching regulator settings */ ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */ #if !defined(CONFIG_ATH_NAND_BR) if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) { if (type == 2) { // ddr1 ar7240_reg_wr_nf(0x18116c44, 0x10000000); /* AR_PHY_PMU2 */ } else { // ddr2 & sdram ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */ } } else { ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */ } #endif wasp_usb_initial_config(); wasp_gpio_config(); reg32 = ar7240_ddr_find_size(); return reg32; }