void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { switch (lane_prtcl) { case QSGMII_A: wriop_init_dpmac(sd, 3, (int)lane_prtcl); wriop_init_dpmac(sd, 4, (int)lane_prtcl); wriop_init_dpmac(sd, 5, (int)lane_prtcl); wriop_init_dpmac(sd, 6, (int)lane_prtcl); break; case QSGMII_B: wriop_init_dpmac(sd, 7, (int)lane_prtcl); wriop_init_dpmac(sd, 8, (int)lane_prtcl); wriop_init_dpmac(sd, 9, (int)lane_prtcl); wriop_init_dpmac(sd, 10, (int)lane_prtcl); break; } }
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; int lane; memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); if (!is_serdes_prtcl_valid(sd, cfg)) printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; #ifdef CONFIG_FSL_MC_ENET switch (lane_prtcl) { case QSGMII_A: wriop_init_dpmac(sd, 5, (int)lane_prtcl); wriop_init_dpmac(sd, 6, (int)lane_prtcl); wriop_init_dpmac(sd, 7, (int)lane_prtcl); wriop_init_dpmac(sd, 8, (int)lane_prtcl); break; case QSGMII_B: wriop_init_dpmac(sd, 1, (int)lane_prtcl); wriop_init_dpmac(sd, 2, (int)lane_prtcl); wriop_init_dpmac(sd, 3, (int)lane_prtcl); wriop_init_dpmac(sd, 4, (int)lane_prtcl); break; case QSGMII_C: wriop_init_dpmac(sd, 13, (int)lane_prtcl); wriop_init_dpmac(sd, 14, (int)lane_prtcl); wriop_init_dpmac(sd, 15, (int)lane_prtcl); wriop_init_dpmac(sd, 16, (int)lane_prtcl); break; case QSGMII_D: wriop_init_dpmac(sd, 9, (int)lane_prtcl); wriop_init_dpmac(sd, 10, (int)lane_prtcl); wriop_init_dpmac(sd, 11, (int)lane_prtcl); wriop_init_dpmac(sd, 12, (int)lane_prtcl); break; default: if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16) wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); break; } #endif } } }