void trap_init(ulong reloc_addr) { unsigned long ebase = gd->irq_sp; set_handler(0x180, &except_vec3_generic, 0x80); set_handler(0x280, &except_vec_ejtag_debug, 0x80); write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier(); }
static void paravirt_init_secondary(void) { unsigned int sr; sr = set_c0_status(ST0_BEV); write_c0_ebase((u32)ebase); sr |= STATUSF_IP2; /* Interrupt controller on IP2 */ write_c0_status(sr); irq_cpu_online(); }
/** * After we've done initial boot, this function is called to allow the * board code to clean up state, if needed */ static void octeon_init_secondary(void) { unsigned int sr; sr = set_c0_status(ST0_BEV); write_c0_ebase((u32)ebase); write_c0_status(sr); octeon_check_cpu_bist(); octeon_init_cvmcount(); octeon_irq_setup_secondary(); }
unsigned long brcm_setup_ebase(void) { /* * BMIPS5000 is similar to BMIPS4380, but it uses different * configuration registers with different semantics: * * 8000_0000 - new reset/NMI vector (was: bfc0_0000) * 8000_1000 - new !BEV exception base (was: 8000_0000) * * The initial reset/NMI vector for TP1 is at a000_0000 because * CP0 CONFIG comes up in an undefined state, but it is almost * immediately moved down to kseg0. */ unsigned long ebase = 0x80001000; write_c0_brcm_bootvec(0xa0088008); write_c0_ebase(ebase); return ebase; }