/*
* Check a 2D array access operation for exception conditions.
*/
static void Check2DArrayAccess(MDUnroll *unroll, int reg, int reg2, int reg3,
unsigned char *pc, unsigned char *label)
{
#ifndef IL_USE_INTERRUPT_BASED_NULL_POINTER_CHECKS
unsigned char *patch1;
#endif
unsigned char *patch2;
unsigned char *patch3;
#ifndef IL_USE_INTERRUPT_BASED_NULL_POINTER_CHECKS
/* Check the array reference against NULL */
x86_alu_reg_reg(unroll->out, X86_OR, reg, reg);
patch1 = unroll->out;
x86_branch8(unroll->out, X86_CC_EQ, 0, 0);
#endif
/* Check the array bounds */
x86_alu_reg_membase(unroll->out, X86_SUB, reg2, reg, 12);
x86_alu_reg_membase(unroll->out, X86_CMP, reg2, reg, 16);
patch2 = unroll->out;
x86_branch32(unroll->out, X86_CC_LT, 0, 0);
x86_alu_reg_membase(unroll->out, X86_ADD, reg2, reg, 12);
patch3 = unroll->out;
x86_jump8(unroll->out, 0);
x86_patch(patch2, unroll->out);
x86_alu_reg_membase(unroll->out, X86_SUB, reg3, reg, 24);
x86_alu_reg_membase(unroll->out, X86_CMP, reg3, reg, 28);
patch2 = unroll->out;
x86_branch32(unroll->out, X86_CC_LT, 0, 0);
x86_alu_reg_membase(unroll->out, X86_ADD, reg2, reg, 12);
x86_alu_reg_membase(unroll->out, X86_ADD, reg3, reg, 28);
/* Re-execute the current instruction in the interpreter */
#ifndef IL_USE_INTERRUPT_BASED_NULL_POINTER_CHECKS
x86_patch(patch1, unroll->out);
#endif
x86_patch(patch3, unroll->out);
ReExecute(unroll, pc, label);
/* Compute the address of the array element */
x86_patch(patch2, unroll->out);
x86_imul_reg_membase(unroll->out, reg2, reg, 20);
x86_imul_reg_membase(unroll->out, reg3, reg, 32);
x86_alu_reg_reg(unroll->out, X86_ADD, reg2, reg3);
x86_imul_reg_membase(unroll->out, reg2, reg, 4);
x86_mov_reg_membase(unroll->out, reg, reg, 8, 4);
x86_alu_reg_reg(unroll->out, X86_ADD, reg, reg2);
}
gpointer
mono_arch_get_gsharedvt_trampoline (MonoTrampInfo **info, gboolean aot)
{
guint8 *code, *buf;
int buf_len, cfa_offset;
GSList *unwind_ops = NULL;
MonoJumpInfo *ji = NULL;
guint8 *br_out, *br [16];
int info_offset, mrgctx_offset;
buf_len = 320;
buf = code = mono_global_codeman_reserve (buf_len);
/*
* This trampoline is responsible for marshalling calls between normal code and gsharedvt code. The
* caller is a normal or gshared method which uses the signature of the inflated method to make the call, while
* the callee is a gsharedvt method which has a signature which uses valuetypes in place of type parameters, i.e.
* caller:
* foo<bool> (bool b)
* callee:
* T=<type used to represent vtype type arguments, currently TypedByRef>
* foo<T> (T b)
* The trampoline is responsible for marshalling the arguments and marshalling the result back. To simplify
* things, we create our own stack frame, and do most of the work in a C function, which receives a
* GSharedVtCallInfo structure as an argument. The structure should contain information to execute the C function to
* be as fast as possible. The argument is received in EAX from a gsharedvt trampoline. So the real
* call sequence looks like this:
* caller -> gsharedvt trampoline -> gsharevt in trampoline -> start_gsharedvt_call
* FIXME: Optimize this.
*/
cfa_offset = sizeof (gpointer);
mono_add_unwind_op_def_cfa (unwind_ops, code, buf, X86_ESP, cfa_offset);
mono_add_unwind_op_offset (unwind_ops, code, buf, X86_NREG, -cfa_offset);
x86_push_reg (code, X86_EBP);
cfa_offset += sizeof (gpointer);
mono_add_unwind_op_def_cfa_offset (unwind_ops, code, buf, cfa_offset);
mono_add_unwind_op_offset (unwind_ops, code, buf, X86_EBP, - cfa_offset);
x86_mov_reg_reg (code, X86_EBP, X86_ESP, sizeof (gpointer));
mono_add_unwind_op_def_cfa_reg (unwind_ops, code, buf, X86_EBP);
/* Alloc stack frame/align stack */
x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
info_offset = -4;
mrgctx_offset = - 8;
/* The info struct is put into EAX by the gsharedvt trampoline */
/* Save info struct addr */
x86_mov_membase_reg (code, X86_EBP, info_offset, X86_EAX, 4);
/* Save rgctx */
x86_mov_membase_reg (code, X86_EBP, mrgctx_offset, MONO_ARCH_RGCTX_REG, 4);
/* Allocate stack area used to pass arguments to the method */
x86_mov_reg_membase (code, X86_EAX, X86_EAX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, stack_usage), sizeof (gpointer));
x86_alu_reg_reg (code, X86_SUB, X86_ESP, X86_EAX);
#if 0
/* Stack alignment check */
x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
x86_breakpoint (code);
#endif
/* ecx = caller argument area */
x86_mov_reg_reg (code, X86_ECX, X86_EBP, 4);
x86_alu_reg_imm (code, X86_ADD, X86_ECX, 8);
/* eax = callee argument area */
x86_mov_reg_reg (code, X86_EAX, X86_ESP, 4);
/* Call start_gsharedvt_call */
/* Arg 4 */
x86_push_membase (code, X86_EBP, mrgctx_offset);
/* Arg3 */
x86_push_reg (code, X86_EAX);
/* Arg2 */
x86_push_reg (code, X86_ECX);
/* Arg1 */
x86_push_membase (code, X86_EBP, info_offset);
if (aot) {
code = mono_arch_emit_load_aotconst (buf, code, &ji, MONO_PATCH_INFO_JIT_ICALL_ADDR, "mono_x86_start_gsharedvt_call");
x86_call_reg (code, X86_EAX);
} else {
x86_call_code (code, mono_x86_start_gsharedvt_call);
}
x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4 * 4);
/* The address to call is in eax */
/* The stack is now setup for the real call */
/* Load info struct */
x86_mov_reg_membase (code, X86_ECX, X86_EBP, info_offset, 4);
/* Load rgctx */
x86_mov_reg_membase (code, MONO_ARCH_RGCTX_REG, X86_EBP, mrgctx_offset, sizeof (gpointer));
/* Make the call */
x86_call_reg (code, X86_EAX);
/* The return value is either in registers, or stored to an area beginning at sp [info->vret_slot] */
/* EAX/EDX might contain the return value, only ECX is free */
/* Load info struct */
x86_mov_reg_membase (code, X86_ECX, X86_EBP, info_offset, 4);
/* Branch to the in/out handling code */
x86_alu_membase_imm (code, X86_CMP, X86_ECX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, gsharedvt_in), 1);
br_out = code;
x86_branch32 (code, X86_CC_NE, 0, TRUE);
/*
* IN CASE
*/
/* Load ret marshal type */
x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, ret_marshal), 4);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_NONE);
br [0] = code;
x86_branch8 (code, X86_CC_NE, 0, TRUE);
/* Normal return, no marshalling required */
x86_leave (code);
x86_ret (code);
/* Return value marshalling */
x86_patch (br [0], code);
/* Load info struct */
x86_mov_reg_membase (code, X86_EAX, X86_EBP, info_offset, 4);
/* Load 'vret_slot' */
x86_mov_reg_membase (code, X86_EAX, X86_EAX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, vret_slot), 4);
/* Compute ret area address */
x86_shift_reg_imm (code, X86_SHL, X86_EAX, 2);
x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_ESP);
/* The callee does a ret $4, so sp is off by 4 */
x86_alu_reg_imm (code, X86_SUB, X86_EAX, sizeof (gpointer));
/* Branch to specific marshalling code */
// FIXME: Move the I4 case to the top */
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_DOUBLE_FPSTACK);
br [1] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_FLOAT_FPSTACK);
br [2] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_STACK_POP);
br [3] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_I1);
br [4] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_U1);
br [5] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_I2);
br [6] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_U2);
br [7] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
/* IREGS case */
/* Load both eax and edx for simplicity */
x86_mov_reg_membase (code, X86_EDX, X86_EAX, sizeof (gpointer), sizeof (gpointer));
x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0, sizeof (gpointer));
x86_leave (code);
x86_ret (code);
/* DOUBLE_FPSTACK case */
x86_patch (br [1], code);
x86_fld_membase (code, X86_EAX, 0, TRUE);
x86_jump8 (code, 0);
x86_leave (code);
x86_ret (code);
/* FLOAT_FPSTACK case */
x86_patch (br [2], code);
x86_fld_membase (code, X86_EAX, 0, FALSE);
x86_leave (code);
x86_ret (code);
/* STACK_POP case */
x86_patch (br [3], code);
x86_leave (code);
x86_ret_imm (code, 4);
/* I1 case */
x86_patch (br [4], code);
x86_widen_membase (code, X86_EAX, X86_EAX, 0, TRUE, FALSE);
x86_leave (code);
x86_ret (code);
/* U1 case */
x86_patch (br [5], code);
x86_widen_membase (code, X86_EAX, X86_EAX, 0, FALSE, FALSE);
x86_leave (code);
x86_ret (code);
/* I2 case */
x86_patch (br [6], code);
x86_widen_membase (code, X86_EAX, X86_EAX, 0, TRUE, TRUE);
x86_leave (code);
x86_ret (code);
/* U2 case */
x86_patch (br [7], code);
x86_widen_membase (code, X86_EAX, X86_EAX, 0, FALSE, TRUE);
x86_leave (code);
x86_ret (code);
/*
* OUT CASE
*/
x86_patch (br_out, code);
/* Load ret marshal type into ECX */
x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, ret_marshal), 4);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_NONE);
br [0] = code;
x86_branch8 (code, X86_CC_NE, 0, TRUE);
/* Normal return, no marshalling required */
x86_leave (code);
x86_ret (code);
/* Return value marshalling */
x86_patch (br [0], code);
/* EAX might contain the return value */
// FIXME: Use moves
x86_push_reg (code, X86_EAX);
/* Load info struct */
x86_mov_reg_membase (code, X86_EAX, X86_EBP, info_offset, 4);
/* Load 'vret_arg_slot' */
x86_mov_reg_membase (code, X86_EAX, X86_EAX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, vret_arg_slot), 4);
/* Compute ret area address in the caller frame in EAX */
x86_shift_reg_imm (code, X86_SHL, X86_EAX, 2);
x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EBP);
x86_alu_reg_imm (code, X86_ADD, X86_EAX, 8);
x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0, sizeof (gpointer));
/* Branch to specific marshalling code */
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_DOUBLE_FPSTACK);
br [1] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_FLOAT_FPSTACK);
br [2] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_STACK_POP);
br [3] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
x86_alu_reg_imm (code, X86_CMP, X86_ECX, GSHAREDVT_RET_IREGS);
br [4] = code;
x86_branch8 (code, X86_CC_E, 0, TRUE);
/* IREG case */
x86_mov_reg_reg (code, X86_ECX, X86_EAX, sizeof (gpointer));
x86_pop_reg (code, X86_EAX);
x86_mov_membase_reg (code, X86_ECX, 0, X86_EAX, sizeof (gpointer));
x86_leave (code);
x86_ret_imm (code, 4);
/* IREGS case */
x86_patch (br [4], code);
x86_mov_reg_reg (code, X86_ECX, X86_EAX, sizeof (gpointer));
x86_pop_reg (code, X86_EAX);
x86_mov_membase_reg (code, X86_ECX, sizeof (gpointer), X86_EDX, sizeof (gpointer));
x86_mov_membase_reg (code, X86_ECX, 0, X86_EAX, sizeof (gpointer));
x86_leave (code);
x86_ret_imm (code, 4);
/* DOUBLE_FPSTACK case */
x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
x86_patch (br [1], code);
x86_fst_membase (code, X86_EAX, 0, TRUE, TRUE);
x86_jump8 (code, 0);
x86_leave (code);
x86_ret_imm (code, 4);
/* FLOAT_FPSTACK case */
x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
x86_patch (br [2], code);
x86_fst_membase (code, X86_EAX, 0, FALSE, TRUE);
x86_leave (code);
x86_ret_imm (code, 4);
/* STACK_POP case */
x86_patch (br [3], code);
x86_leave (code);
x86_ret_imm (code, 4);
g_assert ((code - buf) < buf_len);
if (info)
*info = mono_tramp_info_create ("gsharedvt_trampoline", buf, code - buf, ji, unwind_ops);
mono_arch_flush_icache (buf, code - buf);
return buf;
}
gpointer
mono_arch_get_gsharedvt_trampoline (MonoTrampInfo **info, gboolean aot)
{
guint8 *code, *buf;
int buf_len, cfa_offset;
GSList *unwind_ops = NULL;
MonoJumpInfo *ji = NULL;
int n_arg_regs, n_arg_fregs, framesize, i;
int info_offset, offset, rgctx_arg_reg_offset;
int caller_reg_area_offset, callee_reg_area_offset, callee_stack_area_offset;
guint8 *br_out, *br [64], *br_ret [64];
int b_ret_index;
int reg_area_size;
buf_len = 2048;
buf = code = mono_global_codeman_reserve (buf_len + MONO_MAX_TRAMPOLINE_UNWINDINFO_SIZE);
/*
* We are being called by an gsharedvt arg trampoline, the info argument is in AMD64_RAX.
*/
n_arg_regs = PARAM_REGS;
n_arg_fregs = FLOAT_PARAM_REGS;
/* Compute stack frame size and offsets */
offset = 0;
/* info reg */
info_offset = offset;
offset += 8;
/* rgctx reg */
rgctx_arg_reg_offset = offset;
offset += 8;
/*callconv in regs */
caller_reg_area_offset = offset;
reg_area_size = ALIGN_TO ((n_arg_regs + n_arg_fregs) * 8, MONO_ARCH_FRAME_ALIGNMENT);
offset += reg_area_size;
framesize = offset;
g_assert (framesize % MONO_ARCH_FRAME_ALIGNMENT == 0);
g_assert (reg_area_size % MONO_ARCH_FRAME_ALIGNMENT == 0);
/* unwind markers 1/3 */
cfa_offset = sizeof (gpointer);
mono_add_unwind_op_def_cfa (unwind_ops, code, buf, AMD64_RSP, cfa_offset);
mono_add_unwind_op_offset (unwind_ops, code, buf, AMD64_RIP, -cfa_offset);
/* save the old frame pointer */
amd64_push_reg (code, AMD64_RBP);
/* unwind markers 2/3 */
cfa_offset += sizeof (gpointer);
mono_add_unwind_op_def_cfa_offset (unwind_ops, code, buf, cfa_offset);
mono_add_unwind_op_offset (unwind_ops, code, buf, AMD64_RBP, - cfa_offset);
/* set it as the new frame pointer */
amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
/* unwind markers 3/3 */
mono_add_unwind_op_def_cfa_reg (unwind_ops, code, buf, AMD64_RBP);
mono_add_unwind_op_fp_alloc (unwind_ops, code, buf, AMD64_RBP, 0);
/* setup the frame */
amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, framesize);
/* save stuff */
/* save info */
amd64_mov_membase_reg (code, AMD64_RSP, info_offset, AMD64_RAX, sizeof (mgreg_t));
/* save rgctx */
amd64_mov_membase_reg (code, AMD64_RSP, rgctx_arg_reg_offset, MONO_ARCH_RGCTX_REG, sizeof (mgreg_t));
for (i = 0; i < n_arg_regs; ++i)
amd64_mov_membase_reg (code, AMD64_RSP, caller_reg_area_offset + i * 8, param_regs [i], sizeof (mgreg_t));
for (i = 0; i < n_arg_fregs; ++i)
amd64_sse_movsd_membase_reg (code, AMD64_RSP, caller_reg_area_offset + (i + n_arg_regs) * 8, i);
/* TODO Allocate stack area used to pass arguments to the method */
/* Allocate callee register area just below the caller area so it can be accessed from start_gsharedvt_call using negative offsets */
/* XXX figure out alignment */
callee_reg_area_offset = reg_area_size - ((n_arg_regs + n_arg_fregs) * 8); /* Ensure alignment */
callee_stack_area_offset = callee_reg_area_offset + reg_area_size;
amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, reg_area_size);
/* Allocate stack area used to pass arguments to the method */
amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, MONO_STRUCT_OFFSET (GSharedVtCallInfo, stack_usage), 4);
amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, AMD64_R11);
/* The stack now looks like this:
<caller stack params area>
<return address>
<old frame pointer>
<caller registers area>
<rgctx>
<gsharedvt info>
<callee stack area>
<callee reg area>
*/
/* Call start_gsharedvt_call () */
/* arg1 == info */
amd64_mov_reg_reg (code, MONO_AMD64_ARG_REG1, AMD64_RAX, sizeof(mgreg_t));
/* arg2 = caller stack area */
amd64_lea_membase (code, MONO_AMD64_ARG_REG2, AMD64_RBP, -(framesize - caller_reg_area_offset));
/* arg3 == callee stack area */
amd64_lea_membase (code, MONO_AMD64_ARG_REG3, AMD64_RSP, callee_reg_area_offset);
/* arg4 = mrgctx reg */
amd64_mov_reg_reg (code, MONO_AMD64_ARG_REG4, MONO_ARCH_RGCTX_REG, sizeof(mgreg_t));
if (aot) {
code = mono_arch_emit_load_aotconst (buf, code, &ji, MONO_PATCH_INFO_JIT_ICALL_ADDR, "mono_amd64_start_gsharedvt_call");
#ifdef TARGET_WIN32
/* Since we are doing a call as part of setting up stackframe, the reserved shadow stack used by Windows platform is allocated up in
the callee stack area but currently the callee reg area is in between. Windows calling convention dictates that room is made on stack where
callee can save any parameters passed in registers. Since Windows x64 calling convention
uses 4 registers for the first 4 parameters, stack needs to be adjusted before making the call.
NOTE, Windows calling convention assumes that space for all registers have been reserved, regardless
of the number of function parameters actually used.
*/
int shadow_reg_size = 0;
shadow_reg_size = ALIGN_TO (PARAM_REGS * sizeof(gpointer), MONO_ARCH_FRAME_ALIGNMENT);
amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, shadow_reg_size);
amd64_call_reg (code, AMD64_R11);
amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, shadow_reg_size);
#else
amd64_call_reg (code, AMD64_R11);
#endif
} else {
amd64_call_code (code, mono_amd64_start_gsharedvt_call);
}
/* Method to call is now on RAX. Restore regs and jump */
amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, sizeof(mgreg_t));
for (i = 0; i < n_arg_regs; ++i)
amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, callee_reg_area_offset + i * 8, sizeof (mgreg_t));
for (i = 0; i < n_arg_fregs; ++i)
amd64_sse_movsd_reg_membase (code, i, AMD64_RSP, callee_reg_area_offset + (i + n_arg_regs) * 8);
//load rgctx
amd64_mov_reg_membase (code, MONO_ARCH_RGCTX_REG, AMD64_RBP, -(framesize - rgctx_arg_reg_offset), sizeof (mgreg_t));
/* Clear callee reg area */
amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, reg_area_size);
/* Call the thing */
amd64_call_reg (code, AMD64_R11);
/* Marshal return value. Available registers: R10 and R11 */
/* Load info struct */
amd64_mov_reg_membase (code, AMD64_R10, AMD64_RBP, -(framesize - info_offset), sizeof (mgreg_t));
/* Branch to the in/out handling code */
amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R10, MONO_STRUCT_OFFSET (GSharedVtCallInfo, gsharedvt_in), 1, 4);
b_ret_index = 0;
br_out = code;
x86_branch32 (code, X86_CC_NE, 0, TRUE);
/*
* IN CASE
*/
/* Load vret_slot */
/* Use first input parameter register as scratch since it is volatile on all platforms */
amd64_mov_reg_membase (code, MONO_AMD64_ARG_REG1, AMD64_R10, MONO_STRUCT_OFFSET (GSharedVtCallInfo, vret_slot), 4);
amd64_alu_reg_imm (code, X86_SUB, MONO_AMD64_ARG_REG1, n_arg_regs + n_arg_fregs);
amd64_shift_reg_imm (code, X86_SHL, MONO_AMD64_ARG_REG1, 3);
/* vret address is RBP - (framesize - caller_reg_area_offset) */
amd64_mov_reg_reg (code, AMD64_R11, AMD64_RSP, sizeof(mgreg_t));
amd64_alu_reg_reg (code, X86_ADD, AMD64_R11, MONO_AMD64_ARG_REG1);
/* Load ret marshal type */
/* Load vret address in R11 */
amd64_mov_reg_membase (code, AMD64_R10, AMD64_R10, MONO_STRUCT_OFFSET (GSharedVtCallInfo, ret_marshal), 4);
for (i = GSHAREDVT_RET_NONE; i < GSHAREDVT_RET_NUM; ++i) {
amd64_alu_reg_imm (code, X86_CMP, AMD64_R10, i);
br [i] = code;
amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
}
x86_breakpoint (code); /* unhandled case */
for (i = GSHAREDVT_RET_NONE; i < GSHAREDVT_RET_NUM; ++i) {
mono_amd64_patch (br [i], code);
switch (i) {
case GSHAREDVT_RET_NONE:
break;
case GSHAREDVT_RET_I1:
amd64_widen_membase (code, AMD64_RAX, AMD64_R11, 0, TRUE, FALSE);
break;
case GSHAREDVT_RET_U1:
amd64_widen_membase (code, AMD64_RAX, AMD64_R11, 0, FALSE, FALSE);
break;
case GSHAREDVT_RET_I2:
amd64_widen_membase (code, AMD64_RAX, AMD64_R11, 0, TRUE, TRUE);
break;
case GSHAREDVT_RET_U2:
amd64_widen_membase (code, AMD64_RAX, AMD64_R11, 0, FALSE, TRUE);
break;
case GSHAREDVT_RET_I4: // CORRECT
case GSHAREDVT_RET_U4: // THIS IS INCORRECT. WHY IS IT NOT FAILING?
amd64_movsxd_reg_membase (code, AMD64_RAX, AMD64_R11, 0);
break;
case GSHAREDVT_RET_I8:
amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, 0, 8);
break;
case GSHAREDVT_RET_IREGS_1:
amd64_mov_reg_membase (code, return_regs [i - GSHAREDVT_RET_IREGS_1], AMD64_R11, 0, 8);
break;
case GSHAREDVT_RET_R8:
amd64_sse_movsd_reg_membase (code, AMD64_XMM0, AMD64_R11, 0);
break;
default:
x86_breakpoint (code); /* can't handle specific case */
}
br_ret [b_ret_index ++] = code;
x86_jump32 (code, 0);
}
/*
* OUT CASE
*/
mono_amd64_patch (br_out, code);
/*
Address to write return to is in the original value of the register specified by vret_arg_reg.
This will be either RSI, RDI (System V) or RCX, RDX (Windows) depending on whether this is a static call.
Its location:
We alloc 'framesize' bytes below RBP to save regs, info and rgctx. RSP = RBP - framesize
We store RDI (System V), RCX (Windows) at RSP + caller_reg_area_offset + slot_index_of (register) * 8.
address: RBP - framesize + caller_reg_area_offset + 8*slot
*/
int caller_vret_offset = caller_reg_area_offset - framesize;
/* Load vret address in R11 */
/* Position to return to is passed as a hidden argument. Load 'vret_arg_slot' to find it */
amd64_movsxd_reg_membase (code, AMD64_R11, AMD64_R10, MONO_STRUCT_OFFSET (GSharedVtCallInfo, vret_arg_reg));
// In the GSHAREDVT_RET_NONE case, vret_arg_slot is -1. In this case, skip marshalling.
amd64_alu_reg_imm (code, X86_CMP, AMD64_R11, 0);
br_ret [b_ret_index ++] = code;
amd64_branch32 (code, X86_CC_LT, 0, TRUE);
/* Compute ret area address in the caller frame, *( ((gpointer *)RBP) [R11+2] ) */
amd64_shift_reg_imm (code, X86_SHL, AMD64_R11, 3);
amd64_alu_reg_imm (code, X86_ADD, AMD64_R11, caller_vret_offset);
amd64_alu_reg_reg (code, X86_ADD, AMD64_R11, AMD64_RBP);
amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, sizeof (gpointer));
/* Load ret marshal type in R10 */
amd64_mov_reg_membase (code, AMD64_R10, AMD64_R10, MONO_STRUCT_OFFSET (GSharedVtCallInfo, ret_marshal), 4);
// Switch table for ret_marshal value
for (i = GSHAREDVT_RET_NONE; i < GSHAREDVT_RET_NUM; ++i) {
amd64_alu_reg_imm (code, X86_CMP, AMD64_R10, i);
br [i] = code;
amd64_branch8 (code, X86_CC_EQ, 0, TRUE);
}
x86_breakpoint (code); /* unhandled case */
for (i = GSHAREDVT_RET_NONE; i < GSHAREDVT_RET_NUM; ++i) {
mono_amd64_patch (br [i], code);
switch (i) {
case GSHAREDVT_RET_NONE:
break;
case GSHAREDVT_RET_IREGS_1:
amd64_mov_membase_reg (code, AMD64_R11, 0, return_regs [i - GSHAREDVT_RET_IREGS_1], 8);
break;
case GSHAREDVT_RET_R8:
amd64_sse_movsd_membase_reg (code, AMD64_R11, 0, AMD64_XMM0);
break;
default:
x86_breakpoint (code); /* can't handle specific case */
}
br_ret [b_ret_index ++] = code;
x86_jump32 (code, 0);
}
/* exit path */
for (i = 0; i < b_ret_index; ++i)
mono_amd64_patch (br_ret [i], code);
/* Exit code path */
#if TARGET_WIN32
amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
amd64_pop_reg (code, AMD64_RBP);
mono_add_unwind_op_same_value (unwind_ops, code, buf, AMD64_RBP);
#else
amd64_leave (code);
#endif
amd64_ret (code);
g_assert ((code - buf) < buf_len);
g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_MAX_TRAMPOLINE_UNWINDINFO_SIZE));
if (info)
*info = mono_tramp_info_create ("gsharedvt_trampoline", buf, code - buf, ji, unwind_ops);
mono_arch_flush_icache (buf, code - buf);
return buf;
}
/*
* Perform an integer division or remainder.
*/
static void Divide(MDUnroll *unroll, int isSigned, int wantRemainder,
unsigned char *pc, unsigned char *label)
{
#if !defined(IL_USE_INTERRUPT_BASED_INT_DIVIDE_BY_ZERO_CHECKS)
#define IL_NEED_DIVIDE_REEXECUTE 1
unsigned char *patch1;
#endif
#if !defined(IL_USE_INTERRUPT_BASED_INT_OVERFLOW_CHECKS)
#define IL_NEED_DIVIDE_REEXECUTE 1
unsigned char *patch2, *patch3;
#endif
/* Get the arguments into EAX and ECX so we know where they are */
if(unroll->pseudoStackSize != 2 ||
unroll->pseudoStack[0] != X86_EAX ||
unroll->pseudoStack[1] != X86_ECX)
{
FlushRegisterStack(unroll);
unroll->stackHeight -= 8;
x86_mov_reg_membase(unroll->out, X86_EAX, MD_REG_STACK,
unroll->stackHeight, 4);
x86_mov_reg_membase(unroll->out, X86_ECX, MD_REG_STACK,
unroll->stackHeight + 4, 4);
unroll->pseudoStack[0] = X86_EAX;
unroll->pseudoStack[1] = X86_ECX;
unroll->pseudoStackSize = 2;
unroll->regsUsed |= ((1 << X86_EAX) | (1 << X86_ECX));
}
/* Check for conditions that may cause an exception */
#if !defined(IL_USE_INTERRUPT_BASED_INT_DIVIDE_BY_ZERO_CHECKS)
x86_alu_reg_imm(unroll->out, X86_CMP, X86_ECX, 0);
patch1 = unroll->out;
x86_branch8(unroll->out, X86_CC_EQ, 0, 0);
#endif
#if !defined(IL_USE_INTERRUPT_BASED_INT_OVERFLOW_CHECKS)
x86_alu_reg_imm(unroll->out, X86_CMP, X86_ECX, -1);
patch2 = unroll->out;
x86_branch32(unroll->out, X86_CC_NE, 0, 0);
x86_alu_reg_imm(unroll->out, X86_CMP, X86_EAX, (int)0x80000000);
patch3 = unroll->out;
x86_branch32(unroll->out, X86_CC_NE, 0, 0);
#endif
#if !defined(IL_USE_INTERRUPT_BASED_INT_DIVIDE_BY_ZERO_CHECKS)
x86_patch(patch1, unroll->out);
#endif
#if defined(IL_NEED_DIVIDE_REEXECUTE)
/* Re-execute the division instruction to throw the exception */
ReExecute(unroll, pc, label);
#endif
#if !defined(IL_USE_INTERRUPT_BASED_INT_OVERFLOW_CHECKS)
x86_patch(patch2, unroll->out);
x86_patch(patch3, unroll->out);
#endif
/* Perform the division */
if(isSigned)
{
x86_cdq(unroll->out);
}
else
{
x86_clear_reg(unroll->out, X86_EDX);
}
x86_div_reg(unroll->out, X86_ECX, isSigned);
/* Pop ECX from the pseudo stack */
FreeTopRegister(unroll, -1);
/* If we want the remainder, then replace EAX with EDX on the stack */
if(wantRemainder)
{
unroll->pseudoStack[0] = X86_EDX;
unroll->regsUsed = (1 << X86_EDX);
}
}