static void model_106cx_init(struct device *cpu) { char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); /* Update the microcode */ intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ enable_vmx(); /* Configure C States */ configure_c_states(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); /* TODO: PIC thermal sensor control */ /* Start up my CPU siblings */ intel_sibling_init(cpu); }
static void pre_mp_init(void) { x86_mtrr_check(); /* Enable the local cpu apics */ setup_lapic(); }
static void model_6bx_init(device_t cpu) { char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); /* Update the microcode */ intel_update_microcode(microcode_updates); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); #if CONFIG_USBDEBUG // Is this caution really needed? if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); #if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif /* Enable the local cpu apics */ setup_lapic(); }
static void model_10_init(device_t dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); u8 i; msr_t msr; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); disable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } enable_cache(); /* Enable the local cpu apics */ setup_lapic(); /* Set the processor name string */ // init_processor_name(); #if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void c3_init(struct device *dev) { x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); /* Enable the local cpu apics */ setup_lapic(); };
static void model_6xx_init(device_t dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); /* Update the microcode */ intel_update_microcode(microcode_updates); /* Enable the local cpu apics */ setup_lapic(); };
static void model_69x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); /* Update the microcode */ intel_update_microcode_from_cbfs(); /* Enable the local CPU apics */ setup_lapic(); };
static void model_1067x_init(device_t cpu) { char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); /* Update the microcode */ intel_update_microcode(microcode_updates); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); #if CONFIG_USBDEBUG // Is this caution really needed? if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif /* Setup MTRRs */ x86_setup_mtrrs(36); x86_mtrr_check(); #if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif /* Enable the local cpu apics */ setup_lapic(); /* Initialize the APIC timer */ init_timer(); /* Enable virtualization */ enable_vmx(); /* Configure C States */ configure_c_states(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); /* PIC thermal sensor control */ configure_pic_thermal_sensors(); /* Start up my cpu siblings */ intel_sibling_init(cpu); }
static void model_65x_init(device_t dev) { /* Update the microcode */ intel_update_microcode_from_cbfs(); /* Initialize L2 cache */ p6_configure_l2_cache(); /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); /* Enable the local cpu apics */ setup_lapic(); };
void soc_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; void *default_smm_area; uint32_t bsmrwac; printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev)); /* Set up MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(pattrs->address_bits, 2); x86_mtrr_check(); mp_params.num_cpus = pattrs->num_cpus, mp_params.parallel_microcode_load = 1, mp_params.adjust_apic_id = adjust_apic_id; mp_params.flight_plan = &mp_steps[0]; mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; default_smm_area = backup_default_smm_area(); /* * Configure the BUNIT to allow dirty cache line evictions in non-SMM * mode for the lines that were dirtied while in SMM mode. Otherwise * the writes would be silently dropped. */ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); /* Set package MSRs */ reg_script_run(package_msr_script); /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ enable_turbo(); if (mp_init(cpu_bus, &mp_params)) printk(BIOS_ERR, "MP initialization failure.\n"); restore_default_smm_area(default_smm_area); }
static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); if (!intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); /* Update the microcode */ intel_update_microcode(microcode_updates); } /* Enable the local cpu apics */ setup_lapic(); /* Start up my cpu siblings */ intel_sibling_init(cpu); };
static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); if (!intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); /* Update the microcode */ intel_update_microcode_from_cbfs(); } /* Enable the local CPU APICs */ setup_lapic(); /* Start up my CPU siblings */ intel_sibling_init(cpu); };
static void model_68x_init(device_t cpu) { char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); /* Update the microcode */ intel_update_microcode(microcode_updates); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); /* Enable the local cpu apics */ setup_lapic(); }
static void pre_mp_init(void) { uint32_t bsmrwac; /* Set up MTRRs based on physical address size. */ x86_setup_mtrrs_with_detect(); x86_mtrr_check(); /* * Configure the BUNIT to allow dirty cache line evictions in non-SMM * mode for the lines that were dirtied while in SMM mode. Otherwise * the writes would be silently dropped. */ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); /* Set package MSRs */ reg_script_run(package_msr_script); /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ enable_turbo(); }
void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; x86_mtrr_check(); /* Enable the local cpu apics */ setup_lapic(); mp_params.num_cpus = pattrs->num_cpus, mp_params.parallel_microcode_load = 1, mp_params.adjust_apic_id = adjust_apic_id; mp_params.flight_plan = &mp_steps[0]; mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); } }
static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); u8 i; msr_t msr; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache (); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; wrmsr (0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr (msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } /* Enable the local cpu apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { cpu_idx = cpu_info()->index; printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ msr = rdmsr(MSR_SMM_BASE); msr.lo = SMM_BASE - (cpu_idx * 0x400); wrmsr(MSR_SMM_BASE, msr); /* Enable the SMM memory window */ msr = rdmsr(MSR_SMM_MASK); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ wrmsr(MSR_SMM_MASK, msr); } /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); u8 i; msr_t msr; int msrno; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); #if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif PSPProgBar3Msr(NULL); /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void model_14_init(device_t dev) { u32 i; msr_t msr; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif printk(BIOS_DEBUG, "Model 14 Init.\n"); disable_cache (); /* * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. * TODO: * amd_setup_mtrrs(); */ /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); /* Set shadow WB, RdMEM, WrMEM */ msr.lo = msr.hi = 0; wrmsr (0x259, msr); msr.hi = msr.lo = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (i = 0x268; i <= 0x26f; i++) wrmsr(i, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } /* Enable the local cpu apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); printk(BIOS_SPEW, "%s done.\n", __func__); }
static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); u8 i; msr_t msr; int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(MTRR_FIX_64K_00000, msr); wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); if (acpi_is_wakeup()) restore_mtrr(); x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void model_10xxx_init(device_t dev) { u8 i; msr_t msr; struct node_core_id id; #if CONFIG_LOGICAL_CPUS u32 siblings; #endif id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); disable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 5; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } enable_cache(); /* Enable the local cpu apics */ setup_lapic(); /* Set the processor name string */ init_processor_name(); #if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); msr = rdmsr(BU_CFG2_MSR); /* Clear ClLinesToNbDis */ msr.lo &= ~(1 << 15); /* Clear bit 35 as per Erratum 343 */ msr.hi &= ~(1 << (35-32)); wrmsr(BU_CFG2_MSR, msr); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n"); /* Set SMM base address for this CPU */ msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (lapicid() * 0x400); wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ msr = rdmsr(SMM_MASK_MSR); msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ wrmsr(SMM_MASK_MSR, msr); } else { printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n"); /* Set SMM base address for this CPU */ msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (lapicid() * 0x400); wrmsr(SMM_BASE_MSR, msr); /* Disable the SMM memory window */ msr.hi = 0x0; msr.lo = 0x0; wrmsr(SMM_MASK_MSR, msr); } /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }
static void model_12_init(device_t dev) { printk(BIOS_DEBUG, "Model 12 Init.\n"); u8 i; msr_t msr; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif // struct node_core_id id; // id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ // printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); disable_cache(); /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0; i < 5; i++) { wrmsr(MCI_STATUS + (i * 4), msr); } enable_cache(); /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ // init_processor_name(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); }