Esempio n. 1
0
void
__hal_ring_hw_initialize(xge_hal_device_h devh)
{
    xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
    xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
    u64 val64;
    int i, j;

    /* Rx DMA intialization. */

    val64 = 0;
    for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
        if (!hldev->config.ring.queue[i].configured)
            continue;
        val64 |= vBIT(hldev->config.ring.queue[i].priority,
                      (5 + (i * 8)), 3);
    }
    xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
                           &bar0->rx_queue_priority);
    xge_debug_ring(XGE_TRACE, "Rings priority configured to 0x"XGE_OS_LLXFMT,
                   (unsigned long long)val64);

    /* Configuring ring queues according to per-ring configuration */
    val64 = 0;
    for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
        if (!hldev->config.ring.queue[i].configured)
            continue;
        val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
    }
    xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
                           &bar0->rx_queue_cfg);
    xge_debug_ring(XGE_TRACE, "DRAM configured to 0x"XGE_OS_LLXFMT,
                   (unsigned long long)val64);

    if (!hldev->config.rts_qos_en &&
            !hldev->config.rts_port_en &&
            !hldev->config.rts_mac_en) {

        /*
         * Activate default (QoS-based) Rx steering
         */

        val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
                                      &bar0->rts_qos_steering);
        for (j = 0; j < 8 /* QoS max */; j++)
        {
            for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++)
            {
                if (!hldev->config.ring.queue[i].configured)
                    continue;
                if (!hldev->config.ring.queue[i].rth_en)
                    val64 |= (BIT(i) >> (j*8));
            }
        }
        xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
                               &bar0->rts_qos_steering);
        xge_debug_ring(XGE_TRACE, "QoS steering configured to 0x"XGE_OS_LLXFMT,
                       (unsigned long long)val64);

    }
Esempio n. 2
0
static void
__hal_ring_rxdblock_link(xge_hal_mempool_h mempoolh,
                         xge_hal_ring_t *ring, int from, int to)
{
    xge_hal_ring_block_t *to_item, *from_item;
    dma_addr_t to_dma, from_dma;
    pci_dma_h to_dma_handle, from_dma_handle;

    /* get "from" RxD block */
    from_item = (xge_hal_ring_block_t *)
                __hal_mempool_item((xge_hal_mempool_t *) mempoolh, from);
    xge_assert(from_item);

    /* get "to" RxD block */
    to_item = (xge_hal_ring_block_t *)
              __hal_mempool_item((xge_hal_mempool_t *) mempoolh, to);
    xge_assert(to_item);

    /* return address of the beginning of previous RxD block */
    to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);

    /* set next pointer for this RxD block to point on
     * previous item's DMA start address */
    __hal_ring_block_next_pointer_set(from_item, to_dma);

    /* return "from" RxD block's DMA start address */
    from_dma =
        __hal_ring_item_dma_addr(mempoolh, from_item, &from_dma_handle);

#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
    /* we must sync "from" RxD block, so hardware will see it */
    xge_os_dma_sync(ring->channel.pdev,
                    from_dma_handle,
                    from_dma + XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
                    __hal_ring_item_dma_offset(mempoolh, from_item) +
                    XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
                    sizeof(u64),
                    XGE_OS_DMA_DIR_TODEVICE);
#endif

    xge_debug_ring(XGE_TRACE, "block%d:0x"XGE_OS_LLXFMT" => block%d:0x"XGE_OS_LLXFMT,
                   from, (unsigned long long)from_dma, to,
                   (unsigned long long)to_dma);
}
Esempio n. 3
0
void
__hal_ring_hw_initialize(xge_hal_device_h devh)
{
	xge_hal_device_t *hldev = (xge_hal_device_t *)devh;
	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
	u64 val64;
	int i, j;

	/* Rx DMA intialization. */

	val64 = 0;
	for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
		if (!hldev->config.ring.queue[i].configured)
			continue;
		val64 |= vBIT(hldev->config.ring.queue[i].priority,
							(5 + (i * 8)), 3);
	}
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
			&bar0->rx_queue_priority);
	xge_debug_ring(XGE_TRACE, "Rings priority configured to 0x%llx",
			(unsigned long long)val64);

	/* Configuring ring queues according to per-ring configuration */
	val64 = 0;
	for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
		if (!hldev->config.ring.queue[i].configured)
			continue;
		val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
	}
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
	                     &bar0->rx_queue_cfg);
	xge_debug_ring(XGE_TRACE, "DRAM configured to 0x%llx",
			(unsigned long long)val64);

	/* Activate Rx steering */
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	                            &bar0->rts_qos_steering);
	for (j = 0; j < 8 /* QoS max */; j++) {
		for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
			if (!hldev->config.ring.queue[i].configured)
				continue;
			if (!hldev->config.ring.queue[i].rth_en)
				val64 |= (BIT(i) >> (j*8));
		}
	}
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
	                     &bar0->rts_qos_steering);
	xge_debug_ring(XGE_TRACE, "QoS steering configured to 0x%llx",
			(unsigned long long)val64);

	/* Note: If a queue does not exist, it should be assigned a maximum
	 *	 length of zero. Otherwise, packet loss could occur.
	 *	 P. 4-4 User guide.
	 *
	 * All configured rings will be properly set at device open time
	 * by utilizing device_mtu_set() API call. */
	for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
		if (hldev->config.ring.queue[i].configured)
			continue;
		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, 0ULL,
		                     &bar0->rts_frm_len_n[i]);
	}

#ifdef XGE_HAL_HERC_EMULATION
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
		((u8 *)bar0 + 0x2e60)); /* mc_rldram_mrs_herc */
	val64 |= 0x0000000000010000;
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
		((u8 *)bar0 + 0x2e60));

	val64 |= 0x003a000000000000;
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
		((u8 *)bar0 + 0x2e40)); /* mc_rldram_ref_herc */
	xge_os_mdelay(2000);
#endif

	/* now enabling MC-RLDRAM after setting MC_QUEUE sizes */
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	                            &bar0->mc_rldram_mrs);
	val64 |= XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE |
		 XGE_HAL_MC_RLDRAM_MRS_ENABLE;
	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
	                     &bar0->mc_rldram_mrs);
	xge_os_wmb();
	__hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64,
	                     &bar0->mc_rldram_mrs);

	/* RLDRAM initialization procedure require 500us to complete */
	xge_os_mdelay(1);

	/* Temporary fixes for Herc RLDRAM */
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
		val64 = XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(0x0279);
		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
		                     &bar0->mc_rldram_ref_per_herc);

		val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	                            &bar0->mc_rldram_mrs_herc);
		xge_debug_ring(XGE_TRACE, "default mc_rldram_mrs_herc 0x%llx",
			       (unsigned long long)val64);

		val64 = 0x0003570003010300ULL;
		xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
		                       &bar0->mc_rldram_mrs_herc);

		xge_os_mdelay(1);
	}
	xge_debug_ring(XGE_TRACE, "%s", "ring channels initialized");
}
Esempio n. 4
0
void
__hal_ring_prc_enable(xge_hal_channel_h channelh)
{
	xge_hal_ring_t *ring = (xge_hal_ring_t *)channelh;
	xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
	xge_hal_pci_bar0_t *bar0;
	u64 val64;
	void *first_block;
	int block_num;
	xge_hal_ring_queue_t *queue;
	pci_dma_h dma_handle;

	xge_assert(ring);
	xge_assert(ring->channel.pdev);
	bar0 = (xge_hal_pci_bar0_t *) (void *)
			((xge_hal_device_t *)ring->channel.devh)->bar0;

	queue = &ring->config->queue[ring->channel.post_qid];
	xge_assert(queue->buffer_mode == 1 ||
		    queue->buffer_mode == 3 ||
		    queue->buffer_mode == 5);

	/* last block in fact becomes first. This is just the way it
	 * is filled up and linked by item_alloc() */

	block_num = queue->initial;
	first_block = __hal_mempool_item(ring->mempool, block_num - 1);
	val64 = __hal_ring_item_dma_addr(ring->mempool,
					 first_block, &dma_handle);
	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);

	xge_debug_ring(XGE_TRACE, "ring%d PRC DMA addr 0x%llx initialized",
			ring->channel.post_qid, (unsigned long long)val64);

	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
		ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC &&
	    !queue->rth_en) {
		val64 |= XGE_HAL_PRC_CTRL_RTH_DISABLE;
	}
	val64 |= XGE_HAL_PRC_CTRL_RC_ENABLED;

	val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
	val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
	val64 |= XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(
		(hldev->config.pci_freq_mherz * queue->backoff_interval_us));

	/* Beware: no snoop by the bridge if (no_snoop_bits) */
	val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits);

        /* Herc: always use group_reads */
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
	        val64 |= XGE_HAL_PRC_CTRL_GROUP_READS;

	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);

	/* Configure Receive Protocol Assist */
	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
			ring->channel.regh0, &bar0->rx_pa_cfg);
	val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode);
	val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL);
	/* Clean STRIP_VLAN_TAG bit and set as config from upper layer */
	val64 &= ~XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(1);
	val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag);

	xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
			val64, &bar0->rx_pa_cfg);

	xge_debug_ring(XGE_TRACE, "ring%d enabled in buffer_mode %d",
			ring->channel.post_qid, queue->buffer_mode);
}