static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data) { void __iomem *addr, *wr, *cmd, *cmd_done; addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", wr_addr); }
static void xgene_enet_wr_mac(struct xgene_enet_pdata *p, u32 wr_addr, u32 wr_data) { struct xgene_indirect_ctl ctl = { .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET }; if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data)) netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr); } static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) { return ioread32(p->eth_csr_addr + offset); } static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) { return ioread32(p->eth_diag_csr_addr + offset); } static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr) { u32 rd_data; int i; iowrite32(rd_addr, ctl->addr); iowrite32(XGENE_ENET_RD_CMD, ctl->cmd); /* wait for read command to complete */ for (i = 0; i < 10; i++) { if (ioread32(ctl->cmd_done)) { rd_data = ioread32(ctl->ctl); iowrite32(0, ctl->cmd); return rd_data; } udelay(1); } pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr); return 0; }