/* mode set a plane */ int xilinx_drm_plane_mode_set(struct drm_plane *base_plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct drm_gem_cma_object *obj; size_t offset; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); if (fb->pixel_format != plane->format) { DRM_ERROR("unsupported pixel format %08x\n", fb->pixel_format); return -EINVAL; } /* configure cresample */ if (plane->cresample) xilinx_cresample_configure(plane->cresample, crtc_w, crtc_h); /* configure rgb2yuv */ if (plane->rgb2yuv) xilinx_rgb2yuv_configure(plane->rgb2yuv, crtc_w, crtc_h); obj = drm_fb_cma_get_gem_obj(fb, 0); if (!obj) { DRM_ERROR("failed to get a gem obj for fb\n"); return -EINVAL; } DRM_DEBUG_KMS("h: %d(%d), v: %d(%d), paddr: %p\n", src_w, crtc_x, src_h, crtc_y, (void *)obj->paddr); DRM_DEBUG_KMS("bpp: %d\n", fb->bits_per_pixel / 8); /* configure dma desc */ plane->dma.xt.numf = src_h; plane->dma.sgl[0].size = src_w * fb->bits_per_pixel / 8; plane->dma.sgl[0].icg = fb->pitches[0] - plane->dma.sgl[0].size; offset = src_x * fb->bits_per_pixel / 8 + src_y * fb->pitches[0]; plane->dma.xt.src_start = obj->paddr + offset; plane->dma.xt.frame_size = 1; plane->dma.xt.dir = DMA_MEM_TO_DEV; plane->dma.xt.src_sgl = true; plane->dma.xt.dst_sgl = false; /* set OSD dimensions */ if (plane->manager->osd) { xilinx_osd_disable_rue(plane->manager->osd); /* if a plane is private, it's for crtc */ if (plane->priv) xilinx_osd_set_dimension(plane->manager->osd, crtc_w, crtc_h); xilinx_osd_layer_set_dimension(plane->osd_layer, crtc_x, crtc_y, src_w, src_h); xilinx_osd_enable_rue(plane->manager->osd); } return 0; }
/** * xilinx_drm_plane_manager_mode_set - Set the mode to the Xilinx plane manager * @manager: Xilinx plane manager object * @crtc_w: CRTC width * @crtc_h: CRTC height * * Set the width and height of the Xilinx plane manager. This function is uaully * called from the CRTC driver before calling the xilinx_drm_plane_mode_set(). */ void xilinx_drm_plane_manager_mode_set(struct xilinx_drm_plane_manager *manager, unsigned int crtc_w, unsigned int crtc_h) { if (manager->osd) xilinx_osd_set_dimension(manager->osd, crtc_w, crtc_h); }
/* mode set a plane */ int xilinx_drm_plane_mode_set(struct drm_plane *base_plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct drm_gem_cma_object *obj; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); if (fb->pixel_format != plane->format) { DRM_ERROR("unsupported pixel format %08x\n", fb->pixel_format); return -EINVAL; } /* configure cresample */ if (plane->cresample) xilinx_cresample_configure(plane->cresample, crtc_w, crtc_h); /* configure rgb2yuv */ if (plane->rgb2yuv) xilinx_rgb2yuv_configure(plane->rgb2yuv, crtc_w, crtc_h); obj = drm_fb_cma_get_gem_obj(fb, 0); if (!obj) { DRM_ERROR("failed to get a gem obj for fb\n"); return -EINVAL; } plane->x = src_x; plane->y = src_y; plane->bpp = fb->bits_per_pixel / 8; plane->paddr = obj->paddr; DRM_DEBUG_KMS("h: %d(%d), v: %d(%d), paddr: %p\n", src_w, crtc_x, src_h, crtc_y, (void *)obj->paddr); DRM_DEBUG_KMS("bpp: %d\n", plane->bpp); /* configure vdma desc */ plane->vdma.dma_config.hsize = src_w * plane->bpp; plane->vdma.dma_config.vsize = src_h; plane->vdma.dma_config.stride = fb->pitches[0]; plane->vdma.dma_config.park = 1; plane->vdma.dma_config.park_frm = 0; dmaengine_device_control(plane->vdma.chan, DMA_SLAVE_CONFIG, (unsigned long)&plane->vdma.dma_config); /* set OSD dimensions */ if (plane->manager->osd) { xilinx_osd_disable_rue(plane->manager->osd); /* if a plane is private, it's for crtc */ if (plane->priv) xilinx_osd_set_dimension(plane->manager->osd, crtc_w, crtc_h); xilinx_osd_layer_set_dimension(plane->osd_layer, crtc_x, crtc_y, src_w, src_h); xilinx_osd_enable_rue(plane->manager->osd); } return 0; }