void test_xorlw_with_valid_operand1_0x0A_should_xor_to_WREG_return_0xBF(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with 0x0A
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0x0A,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x03
};
FSR[WREG] = 0xB5;
//00001010 -> 0A
//10110101 -> B5
//10111111 -> BF
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xBF,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x04,code.absoluteAddress);
}
void test_xorlw_with_non_empty_operand3_ACCESS_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with 0x0A
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0x0A,
.operand2 = -1,
.operand3 = ACCESS,
.absoluteAddress = 0x0A
};
FSR[WREG] = 0xB5;
//00001010 -> 0A
//10110101 -> B5
//10111111 -> BF
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND3,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x0A,code.absoluteAddress);
}
void test_xorlw_with_valid_operand1_0xA5_should_xor_to_WREG_return_0x20_and_do_not_set_any_flag_in_STATUS_REG(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with A5h and XOR with 0x0A
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 0xA5,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x11
};
FSR[WREG] = 0x85;
//10100101 -> A5
//10000101 -> 85
//00100000 -> 20
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0x20,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x00,FSR[STATUS]);
TEST_ASSERT_EQUAL_HEX8(0x12,code.absoluteAddress);
}
void test_xorlw_given_eight_bit_Literal_XOR_with_WREG_result_should_store_into_WREG(void)
{
int Literal = 0x6D;
WREG = 0x29;
xorlw (Literal);
TEST_ASSERT_EQUAL(0x44, WREG);
}
void test_xorlw_with_invalid_operand1_256_should_throw_exception(){
CEXCEPTION_T operandERR;
//Test fixture
//Initialize WREG with B5h and XOR with 256
Bytecode code = {.instruction = {.mnemonic = XORLW, .name = "xorlw"},
.operand1 = 256,
.operand2 = -1,
.operand3 = -1,
.absoluteAddress = 0x02
};
FSR[WREG] = 0xB5;
Try{
xorlw(&code);
} Catch(operandERR){
TEST_ASSERT_EQUAL(ERR_INVALID_OPERAND1,operandERR);
}
TEST_ASSERT_EQUAL_HEX8(0xB5,FSR[WREG]);
TEST_ASSERT_EQUAL_HEX8(0x02,code.absoluteAddress);
}
