static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
int remaining_words; /* the number of words left to transfer */
bool use_irq = false;
u16 cr = 0;
/* We get here with transmitter inhibited */
xspi->tx_ptr = t->tx_buf;
xspi->rx_ptr = t->rx_buf;
remaining_words = t->len / xspi->bytes_per_word;
if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
u32 isr;
use_irq = true;
/* Inhibit irq to avoid spurious irqs on tx_empty*/
cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
xspi->regs + XSPI_CR_OFFSET);
/* ACK old irqs (if any) */
isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
if (isr)
xspi->write_fn(isr,
xspi->regs + XIPIF_V123B_IISR_OFFSET);
/* Enable the global IPIF interrupt */
xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
xspi->regs + XIPIF_V123B_DGIER_OFFSET);
reinit_completion(&xspi->done);
}
while (remaining_words) {
int n_words, tx_words, rx_words;
u32 sr;
int stalled;
n_words = min(remaining_words, xspi->buffer_size);
tx_words = n_words;
while (tx_words--)
xilinx_spi_tx(xspi);
/* Start the transfer by not inhibiting the transmitter any
* longer
*/
if (use_irq) {
xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
wait_for_completion(&xspi->done);
/* A transmit has just completed. Process received data
* and check for more data to transmit. Always inhibit
* the transmitter while the Isr refills the transmit
* register/FIFO, or make sure it is stopped if we're
* done.
*/
xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
xspi->regs + XSPI_CR_OFFSET);
sr = XSPI_SR_TX_EMPTY_MASK;
} else
sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
/* Read out all the data from the Rx FIFO */
rx_words = n_words;
stalled = 10;
while (rx_words) {
if (rx_words == n_words && !(stalled--) &&
!(sr & XSPI_SR_TX_EMPTY_MASK) &&
(sr & XSPI_SR_RX_EMPTY_MASK)) {
dev_err(&spi->dev,
"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
xspi_init_hw(xspi);
return -EIO;
}
if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
xilinx_spi_rx(xspi);
rx_words--;
continue;
}
sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
xilinx_spi_rx(xspi);
rx_words--;
}
}
remaining_words -= n_words;
}
if (use_irq) {
xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
}
return t->len;
}
static int xilinx_spi_probe(struct platform_device *pdev)
{
struct xilinx_spi *xspi;
struct xspi_platform_data *pdata;
struct resource *res;
int ret, num_cs = 0, bits_per_word = 8;
struct spi_master *master;
u32 tmp;
u8 i;
pdata = dev_get_platdata(&pdev->dev);
if (pdata) {
num_cs = pdata->num_chipselect;
bits_per_word = pdata->bits_per_word;
} else {
of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
&num_cs);
}
if (!num_cs) {
dev_err(&pdev->dev,
"Missing slave select configuration data\n");
return -EINVAL;
}
master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
if (!master)
return -ENODEV;
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA;
xspi = spi_master_get_devdata(master);
xspi->bitbang.master = master;
xspi->bitbang.chipselect = xilinx_spi_chipselect;
xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
init_completion(&xspi->done);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
xspi->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(xspi->regs)) {
ret = PTR_ERR(xspi->regs);
goto put_master;
}
master->bus_num = pdev->id;
master->num_chipselect = num_cs;
master->dev.of_node = pdev->dev.of_node;
/*
* Detect endianess on the IP via loop bit in CR. Detection
* must be done before reset is sent because incorrect reset
* value generates error interrupt.
* Setup little endian helper functions first and try to use them
* and check if bit was correctly setup or not.
*/
xspi->read_fn = xspi_read32;
xspi->write_fn = xspi_write32;
xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
tmp &= XSPI_CR_LOOP;
if (tmp != XSPI_CR_LOOP) {
xspi->read_fn = xspi_read32_be;
xspi->write_fn = xspi_write32_be;
}
master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
xspi->bits_per_word = bits_per_word;
if (xspi->bits_per_word == 8) {
xspi->tx_fn = xspi_tx8;
xspi->rx_fn = xspi_rx8;
} else if (xspi->bits_per_word == 16) {
xspi->tx_fn = xspi_tx16;
xspi->rx_fn = xspi_rx16;
} else if (xspi->bits_per_word == 32) {
xspi->tx_fn = xspi_tx32;
xspi->rx_fn = xspi_rx32;
} else {
ret = -EINVAL;
goto put_master;
}
/* SPI controller initializations */
xspi_init_hw(xspi);
xspi->irq = platform_get_irq(pdev, 0);
if (xspi->irq < 0) {
ret = xspi->irq;
goto put_master;
}
/* Register for SPI Interrupt */
ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
dev_name(&pdev->dev), xspi);
if (ret)
goto put_master;
ret = spi_bitbang_start(&xspi->bitbang);
if (ret) {
dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
goto put_master;
}
dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
(unsigned long long)res->start, xspi->regs, xspi->irq);
if (pdata) {
for (i = 0; i < pdata->num_devices; i++)
spi_new_device(master, pdata->devices + i);
}
platform_set_drvdata(pdev, master);
return 0;
put_master:
spi_master_put(master);
return ret;
}
static int __init xilinx_spi_of_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct spi_master *master;
struct xilinx_spi *xspi;
struct resource r_irq_struct;
struct resource r_mem_struct;
struct resource *r_irq = &r_irq_struct;
struct resource *r_mem = &r_mem_struct;
int rc = 0;
const u32 *prop;
int len;
/* Get resources(memory, IRQ) associated with the device */
master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi));
if (master == NULL) {
return -ENOMEM;
}
dev_set_drvdata(&ofdev->dev, master);
rc = of_address_to_resource(ofdev->node, 0, r_mem);
if (rc) {
dev_warn(&ofdev->dev, "invalid address\n");
goto put_master;
}
rc = of_irq_to_resource(ofdev->node, 0, r_irq);
if (rc == NO_IRQ) {
dev_warn(&ofdev->dev, "no IRQ found\n");
goto put_master;
}
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA;
xspi = spi_master_get_devdata(master);
xspi->bitbang.master = spi_master_get(master);
xspi->bitbang.chipselect = xilinx_spi_chipselect;
xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
xspi->bitbang.master->setup = xilinx_spi_setup;
init_completion(&xspi->done);
xspi->irq = r_irq->start;
if (!request_mem_region(r_mem->start,
r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) {
rc = -ENXIO;
dev_warn(&ofdev->dev, "memory request failure\n");
goto put_master;
}
xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1);
if (xspi->regs == NULL) {
rc = -ENOMEM;
dev_warn(&ofdev->dev, "ioremap failure\n");
goto release_mem;
}
xspi->irq = r_irq->start;
/* dynamic bus assignment */
master->bus_num = -1;
/* number of slave select bits is required */
prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len);
if (!prop || len < sizeof(*prop)) {
dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n");
goto unmap_io;
}
master->num_chipselect = *prop;
/* SPI controller initializations */
xspi_init_hw(xspi->regs);
/* Register for SPI Interrupt */
rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
if (rc != 0) {
dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq);
goto unmap_io;
}
rc = spi_bitbang_start(&xspi->bitbang);
if (rc != 0) {
dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n");
goto free_irq;
}
dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
(unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq);
/* Add any subnodes on the SPI bus */
of_register_spi_devices(master, ofdev->node);
return rc;
free_irq:
free_irq(xspi->irq, xspi);
unmap_io:
iounmap(xspi->regs);
release_mem:
release_mem_region(r_mem->start, resource_size(r_mem));
put_master:
spi_master_put(master);
return rc;
}
struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
u32 irq, s16 bus_num)
{
struct spi_master *master;
struct xilinx_spi *xspi;
struct xspi_platform_data *pdata = dev->platform_data;
int ret;
if (!pdata) {
dev_err(dev, "No platform data attached\n");
return NULL;
}
master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
if (!master)
return NULL;
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA;
xspi = spi_master_get_devdata(master);
xspi->bitbang.master = spi_master_get(master);
xspi->bitbang.chipselect = xilinx_spi_chipselect;
xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
xspi->bitbang.master->setup = xilinx_spi_setup;
init_completion(&xspi->done);
if (!request_mem_region(mem->start, resource_size(mem),
XILINX_SPI_NAME))
goto put_master;
xspi->regs = ioremap(mem->start, resource_size(mem));
if (xspi->regs == NULL) {
dev_warn(dev, "ioremap failure\n");
goto map_failed;
}
master->bus_num = bus_num;
master->num_chipselect = pdata->num_chipselect;
xspi->mem = *mem;
xspi->irq = irq;
if (pdata->little_endian) {
xspi->read_fn = xspi_read32;
xspi->write_fn = xspi_write32;
} else {
xspi->read_fn = xspi_read32_be;
xspi->write_fn = xspi_write32_be;
}
xspi->bits_per_word = pdata->bits_per_word;
if (xspi->bits_per_word == 8) {
xspi->tx_fn = xspi_tx8;
xspi->rx_fn = xspi_rx8;
} else if (xspi->bits_per_word == 16) {
xspi->tx_fn = xspi_tx16;
xspi->rx_fn = xspi_rx16;
} else if (xspi->bits_per_word == 32) {
xspi->tx_fn = xspi_tx32;
xspi->rx_fn = xspi_rx32;
} else
goto unmap_io;
/* SPI controller initializations */
xspi_init_hw(xspi);
/* Register for SPI Interrupt */
ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
if (ret)
goto unmap_io;
ret = spi_bitbang_start(&xspi->bitbang);
if (ret) {
dev_err(dev, "spi_bitbang_start FAILED\n");
goto free_irq;
}
dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
(unsigned long long)mem->start, xspi->regs, xspi->irq);
return master;
free_irq:
free_irq(xspi->irq, xspi);
unmap_io:
iounmap(xspi->regs);
map_failed:
release_mem_region(mem->start, resource_size(mem));
put_master:
spi_master_put(master);
return NULL;
}
static int __init xilinx_spi_probe(struct platform_device *dev)
{
int ret = 0;
struct spi_master *master;
struct xilinx_spi *xspi;
struct xspi_platform_data *pdata;
struct resource *r;
/* Get resources(memory, IRQ) associated with the device */
master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));
if (master == NULL) {
return -ENOMEM;
}
platform_set_drvdata(dev, master);
pdata = dev->dev.platform_data;
if (pdata == NULL) {
ret = -ENODEV;
goto put_master;
}
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (r == NULL) {
ret = -ENODEV;
goto put_master;
}
xspi = spi_master_get_devdata(master);
xspi->bitbang.master = spi_master_get(master);
xspi->bitbang.chipselect = xilinx_spi_chipselect;
xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
xspi->bitbang.master->setup = xilinx_spi_setup;
init_completion(&xspi->done);
if (!request_mem_region(r->start,
r->end - r->start + 1, XILINX_SPI_NAME)) {
ret = -ENXIO;
goto put_master;
}
xspi->regs = ioremap(r->start, r->end - r->start + 1);
if (xspi->regs == NULL) {
ret = -ENOMEM;
goto put_master;
}
xspi->irq = platform_get_irq(dev, 0);
if (xspi->irq < 0) {
ret = -ENXIO;
goto unmap_io;
}
master->bus_num = pdata->bus_num;
master->num_chipselect = pdata->num_chipselect;
xspi->speed_hz = pdata->speed_hz;
/* SPI controller initializations */
xspi_init_hw(xspi->regs);
/* Register for SPI Interrupt */
ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
if (ret != 0)
goto unmap_io;
ret = spi_bitbang_start(&xspi->bitbang);
if (ret != 0) {
dev_err(&dev->dev, "spi_bitbang_start FAILED\n");
goto free_irq;
}
dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
r->start, (u32)xspi->regs, xspi->irq);
return ret;
free_irq:
free_irq(xspi->irq, xspi);
unmap_io:
iounmap(xspi->regs);
put_master:
spi_master_put(master);
return ret;
}
struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
{
struct spi_master *master;
struct xilinx_spi *xspi;
int ret;
master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
if (!master)
return NULL;
master->mode_bits = SPI_CPOL | SPI_CPHA;
xspi = spi_master_get_devdata(master);
xspi->bitbang.master = spi_master_get(master);
xspi->bitbang.chipselect = xilinx_spi_chipselect;
xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
xspi->bitbang.master->setup = xilinx_spi_setup;
init_completion(&xspi->done);
if (!request_mem_region(mem->start, resource_size(mem),
XILINX_SPI_NAME))
goto put_master;
xspi->regs = ioremap(mem->start, resource_size(mem));
if (xspi->regs == NULL) {
dev_warn(dev, "ioremap failure\n");
goto map_failed;
}
master->bus_num = bus_num;
master->num_chipselect = num_cs;
master->dev.of_node = dev->of_node;
xspi->mem = *mem;
xspi->irq = irq;
if (little_endian) {
xspi->read_fn = xspi_read32;
xspi->write_fn = xspi_write32;
} else {
xspi->read_fn = xspi_read32_be;
xspi->write_fn = xspi_write32_be;
}
xspi->bits_per_word = bits_per_word;
if (xspi->bits_per_word == 8) {
xspi->tx_fn = xspi_tx8;
xspi->rx_fn = xspi_rx8;
} else if (xspi->bits_per_word == 16) {
xspi->tx_fn = xspi_tx16;
xspi->rx_fn = xspi_rx16;
} else if (xspi->bits_per_word == 32) {
xspi->tx_fn = xspi_tx32;
xspi->rx_fn = xspi_rx32;
} else
goto unmap_io;
xspi_init_hw(xspi);
ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
if (ret)
goto unmap_io;
ret = spi_bitbang_start(&xspi->bitbang);
if (ret) {
dev_err(dev, "spi_bitbang_start FAILED\n");
goto free_irq;
}
dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
(unsigned long long)mem->start, xspi->regs, xspi->irq);
return master;
free_irq:
free_irq(xspi->irq, xspi);
unmap_io:
iounmap(xspi->regs);
map_failed:
release_mem_region(mem->start, resource_size(mem));
put_master:
spi_master_put(master);
return NULL;
}
