/* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { XtensaCPU *cpu = XTENSA_CPU(s); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); CPUXtensaState *env = &cpu->env; xcc->parent_reset(s); env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; env->sregs[LITBASE] &= ~1; #ifndef CONFIG_USER_ONLY env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->pending_irq_level = 0; #else env->sregs[PS] = (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) | PS_UM | (3 << PS_RING_SHIFT); #endif env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->sregs[CONFIGID0] = env->config->configid[0]; env->sregs[CONFIGID1] = env->config->configid[1]; #ifndef CONFIG_USER_ONLY reset_mmu(env); s->halted = env->runstall; #endif }
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { do_restore_state(retaddr); HELPER(exception_cause_vaddr)( env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } }
static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { XtensaCPU *cpu = xtensa_env_get_cpu(env); if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) && !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { cpu_restore_state(CPU(cpu), retaddr); HELPER(exception_cause_vaddr)(env, env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); } }
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_RELOCATABLE_VECTOR)) { return vector - env->config->vecbase + env->sregs[VECBASE]; } else { return vector; } }
void cpu_reset(CPUXtensaState *env) { env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; env->sregs[LITBASE] &= ~1; env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->pending_irq_level = 0; reset_mmu(env); }
void xtensa_irq_init(CPUXtensaState *env) { XtensaCPU *cpu = xtensa_env_get_cpu(env); env->irq_inputs = (void **)qemu_allocate_irqs( xtensa_set_irq, env, env->config->ninterrupt); if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) && env->config->nccompare > 0) { env->ccompare_timer = qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, cpu); } }
/* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { XtensaCPU *cpu = XTENSA_CPU(s); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); CPUXtensaState *env = &cpu->env; xcc->parent_reset(s); env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; env->sregs[LITBASE] &= ~1; env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->pending_irq_level = 0; reset_mmu(env); }
void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d) { uint32_t old_ccount = env->sregs[CCOUNT]; env->sregs[CCOUNT] += d; if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { int i; for (i = 0; i < env->config->nccompare; ++i) { if (env->sregs[CCOMPARE + i] - old_ccount <= d) { xtensa_timer_irq(env, i, 1); } } } }