int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
unsigned i;
if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
return 0;
}
switch (reg->type) {
case 9: /*pc*/
return gdb_get_reg32(mem_buf, env->pc);
case 1: /*ar*/
xtensa_sync_phys_from_window(env);
return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
% env->config->nareg]);
case 2: /*SR*/
return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
case 3: /*UR*/
return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
case 4: /*f*/
i = reg->targno & 0x0f;
switch (reg->size) {
case 4:
return gdb_get_reg32(mem_buf,
float32_val(env->fregs[i].f32[FP_F32_LOW]));
case 8:
return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
default:
return 0;
}
case 8: /*a*/
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
default:
qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
__func__, n, reg->type);
return 0;
}
}
static void rotate_window_abs(uint32_t position)
{
xtensa_sync_phys_from_window(env);
env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
xtensa_sync_window_from_phys(env);
}
