//WRITE8_DEVICE_HANDLER( ymf262_w )
void ymf262_w(UINT8 ChipID, offs_t offset, UINT8 data)
{
//ymf262_state *info = get_safe_token(device);
ymf262_state *info = &YMF262Data[ChipID];
switch(EMU_CORE)
{
#ifdef ENABLE_ALL_CORES
case EC_MAME:
ymf262_write(info->chip, offset & 3, data);
break;
#endif
case EC_DBOPL:
adlib_OPL3_writeIO(info->chip, offset & 3, data);
break;
}
}
static void UpdateVGM(VGM_PBK* vgmPlay, UINT16 Samples)
{
const dword/*32*/ vgmLen = vgmPlay->file->dataLen;
const UINT8* vgmData = vgmPlay->file->data;
const UINT8* VGMPnt;
dword/*32*/ VGMPos;
dword/*32*/ VGMSmplPos;
UINT8 Command;
UINT8 blockType;
dword/*32*/ blockLen;
vgmPlay->pbSmplPos += Samples;
VGMPos = vgmPlay->vgmPos;
VGMSmplPos = vgmPlay->vgmSmplPos;
while(VGMSmplPos < vgmPlay->pbSmplPos && ! vgmPlay->vgmEnd)
{
VGMPnt = &vgmData[VGMPos];
Command = VGMPnt[0x00];
switch(Command & 0xF0)
{
case 0x70: // small delay (1-16 samples)
VGMSmplPos += (Command & 0x0F) + 0x01;
VGMPos += 0x01;
break;
case 0x80: // DAC write + small delay (0-15 samples)
VGMSmplPos += (Command & 0x0F);
VGMPos += 0x01;
break;
case 0x60:
switch(Command)
{
case 0x66: // End Of File
vgmPlay->vgmPos = VGMPos;
vgmPlay->vgmSmplPos = VGMSmplPos;
if (! DoVgmLoop(vgmPlay))
vgmPlay->vgmEnd = 0x01;
VGMPos = vgmPlay->vgmPos;
VGMSmplPos = vgmPlay->vgmSmplPos;
break;
case 0x62: // 1/60s delay
VGMSmplPos += 735;
VGMPos += 0x01;
break;
case 0x63: // 1/50s delay
VGMSmplPos += 882;
VGMPos += 0x01;
break;
case 0x61: // xx Sample Delay
VGMSmplPos += ReadLE16(&VGMPnt[0x01]);
VGMPos += 0x03;
break;
case 0x67: // Data Block (PCM Data Stream)
blockType = VGMPnt[0x02];
blockLen = ReadLE32(&VGMPnt[0x03]);
blockLen &= 0x7FFFFFFF;
VGMPos += 0x07 + blockLen;
break;
case 0x68: // PCM RAM write
VGMPos += 0x0C;
break;
default:
vgmPlay->vgmEnd = 0x01;
break;
}
break;
case 0x50:
if (Command == 0x50)
{
VGMPos += 0x02; // SN76496 write
break;
}
switch(Command)
{
case 0x51: // YM2413 write
ym2413_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5A: // YM3812 write
ym3812_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5B: // YM3526 write
case 0x5C: // Y8950 write
ym3512_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5E: // YMF262 write, port 0
case 0x5F: // YMF262 write, port 1
ymf262_write(vgmPlay, Command & 0x01, VGMPnt[0x01], VGMPnt[0x02]);
break;
}
VGMPos += 0x03;
break;
case 0x30:
VGMPos += 0x02;
break;
case 0x40:
case 0xA0:
case 0xB0:
VGMPos += 0x03;
break;
case 0xC0:
case 0xD0:
VGMPos += 0x04;
break;
case 0xE0:
case 0xF0:
VGMPos += 0x05;
break;
case 0x90:
switch(Command)
{
case 0x90: // DAC Ctrl: Setup Chip
VGMPos += 0x05;
break;
case 0x91: // DAC Ctrl: Set Data
VGMPos += 0x05;
break;
case 0x92: // DAC Ctrl: Set Freq
VGMPos += 0x06;
break;
case 0x93: // DAC Ctrl: Play from Start Pos
VGMPos += 0x0B;
break;
case 0x94: // DAC Ctrl: Stop immediately
VGMPos += 0x02;
break;
case 0x95: // DAC Ctrl: Play Block (small)
VGMPos += 0x05;
break;
default:
vgmPlay->vgmEnd = 0x01;
break;
}
break;
default:
vgmPlay->vgmEnd = 0x01;
return;
}
if (VGMPos >= vgmLen)
vgmPlay->vgmEnd = 0x01;
}
vgmPlay->vgmPos = VGMPos;
vgmPlay->vgmSmplPos = VGMSmplPos;
if (vgmPlay->vgmEnd)
StopPlayback(vgmPlay);
return;
}