static void
zsnull_softint(struct zs_chanstate *cs)
{
zs_write_reg(cs, 1, 0);
zs_write_reg(cs, 15, 0);
}
void
zscninit(struct consdev *cn)
{
struct zs_chanstate *cs;
extern const struct cdevsw zstty_cdevsw;
cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
zs_conschan = cs = &zs_conschan_store;
/* Setup temporary chanstate. */
cs->cs_reg_csr = zs_cons + ZS_CSR;
cs->cs_reg_data = zs_cons + ZS_DATA;
/* Initialize the pending registers. */
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
cs->cs_preg[13] = 0;
cs->cs_defspeed = ZS_DEFSPEED;
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W */
zs_loadchannelregs(cs);
}
static int
ewskbd_zsc_init(struct zs_chanstate *cs)
{
int s;
s = splzs();
zs_write_reg(cs, 9, ZSWR9_B_RESET);
DELAY(100);
zs_write_reg(cs, 9, ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR);
cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE;
cs->cs_preg[2] = 0;
cs->cs_preg[3] = ZSWR3_RX_8 | ZSWR3_RX_ENABLE;
cs->cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_PARENB;
cs->cs_preg[5] = ZSWR5_TX_8 | ZSWR5_RTS | ZSWR5_TX_ENABLE;
cs->cs_preg[6] = 0;
cs->cs_preg[7] = 0;
cs->cs_preg[8] = 0;
cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR;
cs->cs_preg[10] = 0;
cs->cs_preg[11] = ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD |
ZSWR11_TRXC_OUT_ENA | ZSWR11_TRXC_BAUD;
/* reg[11] and reg[12] are set by zs_set_speed() with cs_brg_clk */
zs_set_speed(cs, EWSKBD_BAUD);
cs->cs_preg[14] = ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA;
cs->cs_preg[15] = 0;
zs_loadchannelregs(cs);
splx(s);
return 0;
}
static void
zs_sbdio_cninit(struct consdev *cn)
{
struct zs_chanstate *cs;
struct zschan *zc;
zc = zs_consaddr;
cs = zs_conscs;
/* Setup temporary chanstate. */
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
/* Initialize the pending registers. */
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_brg_clk = PCLK / 16;
cs->cs_defspeed = ZS_DEFSPEED;
zs_set_speed(cs, ZS_DEFSPEED);
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W */
zs_loadchannelregs(cs);
}
void
zsclock_attach(struct device *parent, struct device *self, void *aux)
{
struct zsc_softc *zsc = (void *)parent;
struct zsclock_softc *sc = (void *)self;
struct zsc_attach_args *args = aux;
struct zs_chanstate *cs;
int channel;
int reset, s, tconst;
channel = args->channel;
cs = &zsc->zsc_cs[channel];
cs->cs_private = zsc;
cs->cs_ops = &zsops_clock;
sc->zsc_cs = cs;
printf("\n");
hz = 100;
tconst = ((PCLK / 2) / hz) - 2;
s = splclock();
reset = (channel == 0) ? ZSWR9_A_RESET : ZSWR9_B_RESET;
zs_write_reg(cs, 9, reset);
cs->cs_preg[1] = 0;
cs->cs_preg[3] = ZSWR3_RX_8 | ZSWR3_RX_ENABLE;
cs->cs_preg[4] = ZSWR4_CLK_X1 | ZSWR4_ONESB | ZSWR4_PARENB;
cs->cs_preg[5] = ZSWR5_TX_8 | ZSWR5_TX_ENABLE;
cs->cs_preg[9] = ZSWR9_MASTER_IE;
cs->cs_preg[10] = 0;
cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC |
ZSWR11_TRXC_OUT_ENA | ZSWR11_TRXC_BAUD;
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
cs->cs_preg[14] = ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA;
cs->cs_preg[15] = ZSWR15_ZERO_COUNT_IE;
zs_loadchannelregs(cs);
splx(s);
/* enable interrupts */
cs->cs_preg[1] |= ZSWR1_SIE;
zs_write_reg(cs, 1, cs->cs_preg[1]);
zsclock_attached = 1;
}
static void
ewskbd_zsc_txint(struct zs_chanstate *cs)
{
struct ewskbd_softc *sc;
sc = cs->cs_private;
zs_write_reg(cs, 0, ZSWR0_RESET_TXINT);
sc->sc_dc->state |= TX_READY;
cs->cs_softreq = 1;
}
static void
zscninit(struct consdev *cn)
{
struct zs_chanstate *cs;
extern const struct cdevsw zstty_cdevsw;
extern int tty00_is_console;
extern uint32_t sccport0a;
cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
if (tty00_is_console)
cn->cn_pri = CN_REMOTE;
else
cn->cn_pri = CN_NORMAL;
zc_cons = (struct zschan *)sccport0a; /* XXX */
zs_conschan = cs = &zs_conschan_store;
/* Setup temporary chanstate. */
cs->cs_reg_csr = &zc_cons->zc_csr;
cs->cs_reg_data = &zc_cons->zc_data;
/* Initialize the pending registers. */
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
cs->cs_preg[13] = 0;
cs->cs_defspeed = 9600;
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W */
zs_loadchannelregs(cs);
}
void
zs_break(struct zs_chanstate *cs, int set)
{
if (set) {
cs->cs_preg[5] |= ZSWR5_BREAK;
cs->cs_creg[5] |= ZSWR5_BREAK;
} else {
cs->cs_preg[5] &= ~ZSWR5_BREAK;
cs->cs_creg[5] &= ~ZSWR5_BREAK;
}
zs_write_reg(cs, 5, cs->cs_creg[5]);
}
void
zscninit(struct consdev *cn)
{
volatile struct zschan *cnchan = (volatile void *)IIOV(ZSCN_PHYSADDR);
int s;
memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
zscn_cs.cs_reg_csr = &cnchan->zc_csr;
zscn_cs.cs_reg_data = &cnchan->zc_data;
zscn_cs.cs_channel = 0;
zscn_cs.cs_brg_clk = PCLK / 16;
memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
zscn_cs.cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
zs_set_speed(&zscn_cs, ZSCN_SPEED);
s = splzs();
zs_write_reg(&zscn_cs, 9, 0);
zs_write_reg(&zscn_cs, 9, ZSWR9_HARD_RESET);
zs_loadchannelregs(&zscn_cs);
splx(s);
conschan = cnchan;
}
/*
* Common parts of console init.
*/
void
zs_cninit(void *base)
{
struct zs_chanstate *cs;
/*
* Pointer to channel state. Later, the console channel
* state is copied into the softc, and the console channel
* pointer adjusted to point to the new copy.
*/
cs = &zs_conschan_store;
zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE;
/* Setup temporary chanstate. */
cs->cs_reg_csr = (uint8_t *)base + 7;
cs->cs_reg_data = (uint8_t *)base + 15;
/* Initialize the pending registers. */
bcopy(zs_init_reg, cs->cs_preg, 16);
cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS);
/* XXX: Preserve BAUD rate from boot loader. */
/* XXX: Also, why reset the chip here? -gwr */
/* cs->cs_defspeed = zs_get_speed(cs); */
cs->cs_defspeed = 9600; /* XXX */
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W. */
zs_loadchannelregs(cs);
/* Point the console at the SCC. */
cn_tab = &zscons;
}
void
zs_shutdown(struct zstty_softc *zst)
{
struct zs_chanstate *cs = zst->zst_cs;
struct tty *tp = zst->zst_tty;
int s;
s = splzs();
/* If we were asserting flow control, then deassert it. */
SET(zst->zst_rx_flags, RX_IBUF_BLOCKED);
zs_hwiflow(zst);
/* Clear any break condition set with TIOCSBRK. */
zs_break(cs, 0);
/* Turn off PPS capture on last close. */
zst->zst_ppsmask = 0;
/*
* Hang up if necessary. Wait a bit, so the other side has time to
* notice even if we immediately open the port again.
*/
if (ISSET(tp->t_cflag, HUPCL) || ISSET(tp->t_state, TS_WOPEN)) {
zs_modem(zst, 0);
/* hold low for 1 second */
(void)tsleep(cs, TTIPRI, ttclos, hz);
}
/* Turn off interrupts if not the console. */
if (!ISSET(zst->zst_hwflags, ZS_HWFLAG_CONSOLE)) {
CLR(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE);
cs->cs_creg[1] = cs->cs_preg[1];
zs_write_reg(cs, 1, cs->cs_creg[1]);
}
/* Call the power management hook. */
if (cs->disable) {
#ifdef DIAGNOSTIC
if (!cs->enabled)
panic("%s: not enabled?", __func__);
#endif
(*cs->disable)(zst->zst_cs);
}
splx(s);
}
/*
* Internal version of zshwiflow
* Called at splzs()
*/
void
zs_hwiflow(struct zstty_softc *zst)
{
struct zs_chanstate *cs = zst->zst_cs, *ccs;
if (cs->cs_wr5_rts == 0)
return;
ccs = (cs->cs_ctl_chan != NULL ? cs->cs_ctl_chan : cs);
if (ISSET(zst->zst_rx_flags, RX_ANY_BLOCK)) {
CLR(ccs->cs_preg[5], cs->cs_wr5_rts);
CLR(ccs->cs_creg[5], cs->cs_wr5_rts);
} else {
SET(ccs->cs_preg[5], cs->cs_wr5_rts);
SET(ccs->cs_creg[5], cs->cs_wr5_rts);
}
zs_write_reg(ccs, 5, ccs->cs_creg[5]);
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct mainbus_attach_args *maa = aux;
struct zsc_attach_args zsc_args;
uint8_t *zs_base;
struct zs_chanstate *cs;
int s, channel;
zsc->zsc_dev = self;
/* XXX: MI z8530 doesn't use bus_space(9) yet */
zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr);
aprint_normal(": optional Z85C30 serial port\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zs_init_reg[2] = 0;
if ((zs_base + chanoff[channel]) == zs_cons) {
memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
zs_conschan = cs;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
} else {
cs->cs_reg_csr = zs_base + chanoff[channel] + ZS_CSR;
cs->cs_reg_data = zs_base + chanoff[channel] + ZS_DATA;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_defspeed = zs_defspeed;
zsc_args.hwflags = 0;
}
zs_lock_init(cs);
cs->cs_defcflag = zs_def_cflag;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splhigh();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc);
zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, 0);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct cfdata *cf = device_cfdata(self);
struct hb_attach_args *ha = aux;
struct zsc_attach_args zsc_args;
struct zsdevice *zs;
struct zschan *zc;
struct zs_chanstate *cs;
int s, channel, clk;
zsc->zsc_dev = self;
zs = (void *)IIOV(ha->ha_address);
clk = cf->cf_flags;
if (clk < 0 || clk >= NPCLK)
clk = 0;
aprint_normal("\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
if (ha->ha_vect != -1)
zs_init_reg[2] = ha->ha_vect;
if (zc == zc_cons) {
memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
zs_conschan = cs;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
} else {
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_defspeed = zs_defspeed;
zsc_args.hwflags = 0;
}
zs_lock_init(cs);
cs->cs_defcflag = zs_def_cflag;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = pclk[clk] / 16;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splhigh();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
/*
* Write the given register set to the given zs channel in the proper order.
* The channel must not be transmitting at the time. The receiver will
* be disabled for the time it takes to write all the registers.
* Call this with interrupts disabled.
*/
void
zs_loadchannelregs(struct zs_chanstate *cs)
{
uint8_t *reg, v;
zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */
#if 1
/*
* XXX: Is this really a good idea?
* XXX: Should go elsewhere! -gwr
*/
zs_iflush(cs); /* XXX */
#endif
if (cs->cs_ctl_chan != NULL)
v = ((cs->cs_ctl_chan->cs_creg[5] & (ZSWR5_RTS | ZSWR5_DTR)) !=
(cs->cs_ctl_chan->cs_preg[5] & (ZSWR5_RTS | ZSWR5_DTR)));
else
v = 0;
if (memcmp((void *)cs->cs_preg, (void *)cs->cs_creg, 16) == 0 && !v)
return; /* only change if values are different */
/* Copy "pending" regs to "current" */
memcpy((void *)cs->cs_creg, (void *)cs->cs_preg, 16);
reg = cs->cs_creg; /* current regs */
/* disable interrupts */
zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);
/* baud clock divisor, stop bits, parity */
zs_write_reg(cs, 4, reg[4]);
/* misc. TX/RX control bits */
zs_write_reg(cs, 10, reg[10]);
/* char size, enable (RX/TX) */
zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
/* synchronous mode stuff */
zs_write_reg(cs, 6, reg[6]);
zs_write_reg(cs, 7, reg[7]);
#if 0
/*
* Registers 2 and 9 are special because they are
* actually common to both channels, but must be
* programmed through channel A. The "zsc" attach
* function takes care of setting these registers
* and they should not be touched thereafter.
*/
/* interrupt vector */
zs_write_reg(cs, 2, reg[2]);
/* master interrupt control */
zs_write_reg(cs, 9, reg[9]);
#endif
/* Shut down the BRG */
zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);
#ifdef ZS_MD_SETCLK
/* Let the MD code setup any external clock. */
ZS_MD_SETCLK(cs);
#endif /* ZS_MD_SETCLK */
/* clock mode control */
zs_write_reg(cs, 11, reg[11]);
/* baud rate (lo/hi) */
zs_write_reg(cs, 12, reg[12]);
zs_write_reg(cs, 13, reg[13]);
/* Misc. control bits */
zs_write_reg(cs, 14, reg[14]);
/* which lines cause status interrupts */
zs_write_reg(cs, 15, reg[15]);
/*
* Zilog docs recommend resetting external status twice at this
* point. Mainly as the status bits are latched, and the first
* interrupt clear might unlatch them to new values, generating
* a second interrupt request.
*/
zs_write_csr(cs, ZSM_RESET_STINT);
zs_write_csr(cs, ZSM_RESET_STINT);
/* char size, enable (RX/TX)*/
zs_write_reg(cs, 3, reg[3]);
zs_write_reg(cs, 5, reg[5]);
/* Write the status bits on the alternate channel also. */
if (cs->cs_ctl_chan != NULL) {
v = cs->cs_ctl_chan->cs_preg[5];
cs->cs_ctl_chan->cs_creg[5] = v;
zs_write_reg(cs->cs_ctl_chan, 5, v);
}
/* interrupt enables: RX, TX, STATUS */
zs_write_reg(cs, 1, reg[1]);
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct confargs *ca = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int s, zs_unit, channel;
static int didintr;
zsc->zsc_dev = self;
zs_unit = device_unit(self);
aprint_normal(": (softpri %d)\n", ZSSOFT_PRI);
/* Use the mapping setup by the Sun PROM. */
if (zsaddr[zs_unit] == NULL)
panic("zs_attach: zs%d not mapped", zs_unit);
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = zs_hwflags[zs_unit][channel];
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zs_lock_init(cs);
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
zc = zs_get_chan_addr(zs_unit, channel);
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
/* XXX: Get these from the EEPROM instead? */
/* XXX: See the mvme167 code. Better. */
if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
cs->cs_defspeed = zs_get_speed(cs);
else
cs->cs_defspeed = zs_defspeed[zs_unit][channel];
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers. Note the arguments
* to the interrupt handlers aren't used. Note, we only do this
* once since both SCCs interrupt at the same level and vector.
*/
if (!didintr) {
didintr = 1;
isr_add_autovect(zshard, NULL, ca->ca_intpri);
}
zsc->zs_si = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/* XXX; evcnt_attach() ? */
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
/*
* XXX: L1A hack - We would like to be able to break into
* the debugger during the rest of autoconfiguration, so
* lower interrupts just enough to let zs interrupts in.
* This is done after both zs devices are attached.
*/
if (zs_unit == 1) {
(void)spl5(); /* splzs - 1 */
}
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
static void
zs_hpc_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct hpc_attach_args *haa = aux;
struct zsc_attach_args zsc_args;
struct zs_chanstate *cs;
struct zs_channel *ch;
int zs_unit, channel, err, s;
const char *promconsdev;
promconsdev = arcbios_GetEnvironmentVariable("ConsoleOut");
zsc->zsc_dev = self;
zsc->zsc_bustag = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff, 0x10,
&zsc->zsc_base)) != 0) {
aprint_error(": unable to map 85c30 registers, error = %d\n",
err);
return;
}
zs_unit = device_unit(self);
aprint_normal("\n");
/*
* Initialize software state for each channel.
*
* Done in reverse order of channels since the first serial port
* is actually attached to the *second* channel, and vice versa.
* Doing it this way should force a 'zstty*' to attach zstty0 to
* channel 1 and zstty1 to channel 0. They couldn't have wired
* it up in a more sensible fashion, could they?
*/
for (channel = 1; channel >= 0; channel--) {
zsc_args.channel = channel;
ch = &zsc->zsc_cs_store[channel];
cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
zs_lock_init(cs);
cs->cs_reg_csr = NULL;
cs->cs_reg_data = NULL;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base,
zs_chan_offset[channel],
sizeof(struct zschan),
&ch->cs_regs) != 0) {
aprint_error_dev(self, "cannot map regs\n");
return;
}
ch->cs_bustag = zsc->zsc_bustag;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
zsc_args.hwflags = 0;
zsc_args.consdev = NULL;
if (zs_consunit == -1 && zs_conschan == -1) {
/*
* If this channel is being used by the PROM console,
* pass the generic zs driver a 'no reset' flag so the
* channel gets left in the appropriate state after
* attach.
*
* Note: the channel mappings are swapped.
*/
if (promconsdev != NULL &&
strlen(promconsdev) == 9 &&
strncmp(promconsdev, "serial", 6) == 0 &&
(promconsdev[7] == '0' || promconsdev[7] == '1')) {
if (promconsdev[7] == '1' && channel == 0)
zsc_args.hwflags |= ZS_HWFLAG_NORESET;
else if (promconsdev[7] == '0' && channel == 1)
zsc_args.hwflags |= ZS_HWFLAG_NORESET;
}
}
/* If console, don't stomp speed, let zstty know */
if (zs_unit == zs_consunit && channel == zs_conschan) {
zsc_args.consdev = &zs_cn;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
cs->cs_defspeed = zs_get_speed(cs);
} else
cs->cs_defspeed = zs_defspeed;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL);
evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
void
zs_ap_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct apbus_attach_args *apa = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int s, zs_unit, channel;
volatile u_int *txBfifo = (void *)(apa->apa_hwbase + PORTB_XPORT);
volatile u_int *rxBfifo = (void *)(apa->apa_hwbase + PORTB_RPORT);
volatile u_int *txAfifo = (void *)(apa->apa_hwbase + PORTA_XPORT);
volatile u_int *rxAfifo = (void *)(apa->apa_hwbase + PORTA_RPORT);
volatile u_int *portBctl = (void *)(apa->apa_hwbase + PORTB_OFFSET);
volatile u_int *portActl = (void *)(apa->apa_hwbase + PORTA_OFFSET);
volatile u_int *esccregs = (void *)(apa->apa_hwbase + ESCC_REG);
zsc->zsc_dev = self;
zs_unit = device_unit(self);
zsaddr[zs_unit] = (void *)apa->apa_hwbase;
aprint_normal(" slot%d addr 0x%lx\n", apa->apa_slotno, apa->apa_hwbase);
txAfifo[DMA_MODE_REG] = rxAfifo[DMA_MODE_REG] = DMA_EXTRDY;
txBfifo[DMA_MODE_REG] = rxBfifo[DMA_MODE_REG] = DMA_EXTRDY;
/* assert DTR */ /* XXX */
portBctl[PORT_CTL] = portActl[PORT_CTL] = PORTCTL_DTR;
/* select RS-232C (ch1 only) */
portActl[PORT_SEL] = PORTSEL_RS232C;
/* enable SCC interrupts */
esccregs[ESCCREG_INTMASK] = INTMASK_SCC;
zs_delay = zs_ap_delay;
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = zs_hwflags[zs_unit][channel];
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zs_lock_init(cs);
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
zc = zs_get_chan_addr(zs_unit, channel);
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
/* XXX: Get these from the EEPROM instead? */
/* XXX: See the mvme167 code. Better. */
if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
cs->cs_defspeed = zs_get_speed(cs);
else
cs->cs_defspeed = zs_defspeed;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
zsc->zsc_si = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */
NEWS5000_INT1_SCC, 0, /* priority */
zshard_ap, zsc, apa->apa_name, apa->apa_ctlnum);
/* XXX; evcnt_attach() ? */
#if 0
{
u_int x;
/* determine SCC/ESCC type */
x = zs_read_reg(cs, 15);
zs_write_reg(cs, 15, x | ZSWR15_ENABLE_ENHANCED);
if (zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) { /* ESCC Z85230 */
zs_write_reg(cs, 7, ZSWR7P_EXTEND_READ | ZSWR7P_TX_FIFO);
}
}
#endif
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
void
zs_config(struct zsc_softc *zsc, char *base)
{
struct zsc_attach_args zsc_args;
struct zs_chanstate *cs;
int zsc_unit, channel, s;
zsc_unit = device_unit(zsc->zsc_dev);
aprint_normal(": Zilog 8530 SCC\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = zs_hwflags[zsc_unit][channel];
/*
* If we're the console, copy the channel state, and
* adjust the console channel pointer.
*/
if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
cs = &zs_conschan_store;
} else {
cs = malloc(sizeof(struct zs_chanstate),
M_DEVBUF, M_NOWAIT | M_ZERO);
if(channel==0){
cs->cs_reg_csr = base + 7;
cs->cs_reg_data = base + 15;
} else {
cs->cs_reg_csr = base + 3;
cs->cs_reg_data = base + 11;
}
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_defspeed = 9600;
}
zsc->zsc_cs[channel] = cs;
zs_lock_init(cs);
cs->cs_defcflag = CREAD | CS8 | HUPCL;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = 4000000 / 16;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(zsc->zsc_dev, (void *)&zsc_args,
zsc_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
}
void
zskbd_txint(struct zs_chanstate *cs)
{
zs_write_reg(cs, 0, ZSWR0_RESET_TXINT);
cs->cs_softreq = 1;
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct intio_attach_args *ia = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int r, s, zs_unit, channel;
zsc->zsc_dev = self;
aprint_normal("\n");
zs_unit = device_unit(self);
zsc->zsc_addr = (void *)ia->ia_addr;
ia->ia_size = 8;
r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
#ifdef DIAGNOSTIC
if (r)
panic("zs: intio IO map corruption");
#endif
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
device_t child;
zsc_args.channel = channel;
zsc_args.hwflags = 0;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zs_lock_init(cs);
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (channel == 0)
zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_a);
else
zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_b);
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
zs_init_reg[2] = ia->ia_intr;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
if (zc == conschan) {
zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
cs->cs_defspeed = zs_get_speed(cs);
cs->cs_defcflag = zscn_def_cflag;
} else {
cs->cs_defspeed = 9600;
cs->cs_defcflag = zs_def_cflag;
}
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splzs();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
child = config_found(self, (void *)&zsc_args, zs_print);
#if ZSTTY > 0
if (zc == conschan &&
((child && strcmp(device_xname(child), "zstty0")) ||
child == NULL)) /* XXX */
panic("%s: console device mismatch", __func__);
#endif
if (child == NULL) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
panic("%s: interrupt vector busy", __func__);
zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/* XXX; evcnt_attach() ? */
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splzs();
/* interrupt vector */
zs_write_reg(cs, 2, ia->ia_intr);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
/*
* Receiver Ready interrupt.
* Called at splzs().
*/
void
zstty_rxint(struct zs_chanstate *cs)
{
struct zstty_softc *zst = cs->cs_private;
uint8_t *put, *end;
u_int cc;
uint8_t rr0, rr1, c;
end = zst->zst_ebuf;
put = zst->zst_rbput;
cc = zst->zst_rbavail;
while (cc > 0) {
/*
* First read the status, because reading the received char
* destroys the status of this char.
*/
rr1 = zs_read_reg(cs, 1);
c = zs_read_data(cs);
if (ISSET(rr1, ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
/* Clear the receive error. */
zs_write_csr(cs, ZSWR0_RESET_ERRORS);
}
put[0] = c;
put[1] = rr1;
put += 2;
if (put >= end)
put = zst->zst_rbuf;
cc--;
rr0 = zs_read_csr(cs);
if (!ISSET(rr0, ZSRR0_RX_READY))
break;
}
/*
* Current string of incoming characters ended because
* no more data was available or we ran out of space.
* Schedule a receive event if any data was received.
* If we're out of space, turn off receive interrupts.
*/
zst->zst_rbput = put;
zst->zst_rbavail = cc;
if (!ISSET(zst->zst_rx_flags, RX_TTY_OVERFLOWED)) {
zst->zst_rx_ready = 1;
cs->cs_softreq = 1;
}
/*
* See if we are in danger of overflowing a buffer. If
* so, use hardware flow control to ease the pressure.
*/
if (!ISSET(zst->zst_rx_flags, RX_IBUF_BLOCKED) &&
cc < zst->zst_r_hiwat) {
SET(zst->zst_rx_flags, RX_IBUF_BLOCKED);
zs_hwiflow(zst);
}
/*
* If we're out of space, disable receive interrupts
* until the queue has drained a bit.
*/
if (!cc) {
SET(zst->zst_rx_flags, RX_IBUF_OVERFLOWED);
CLR(cs->cs_preg[1], ZSWR1_RIE);
cs->cs_creg[1] = cs->cs_preg[1];
zs_write_reg(cs, 1, cs->cs_creg[1]);
}
}
void
zskbd_attach(struct device *parent, struct device *self, void *aux)
{
struct zskbd_softc *sc = (struct zskbd_softc *)self;
struct zsc_softc *zsc = (struct zsc_softc *)parent;
struct zsc_attach_args *args = aux;
struct zs_chanstate *cs;
struct wskbddev_attach_args wskaa;
int s, channel, rc;
uint8_t key;
printf(": ");
/* Establish ourself with the MD z8530 driver */
channel = args->channel;
cs = zsc->zsc_cs[channel];
cs->cs_ops = &zskbd_zsops;
cs->cs_private = sc;
sc->sc_dc = malloc(sizeof(struct zskbd_devconfig), M_DEVBUF,
M_WAITOK | M_ZERO);
s = splzs();
zs_write_reg(cs, 9, (channel == 0) ? ZSWR9_A_RESET : ZSWR9_B_RESET);
cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE;
cs->cs_preg[4] = (cs->cs_preg[4] & ZSWR4_CLK_MASK) |
(ZSWR4_ONESB | ZSWR4_PARENB); /* 1 stop, odd parity */
cs->cs_preg[15] &= ~ZSWR15_ENABLE_ENHANCED;
zs_set_speed(cs, ZSKBD_BAUD);
zs_loadchannelregs(cs);
/*
* Empty the keyboard input buffer (if the keyboard is the console
* input device and the user invoked UKC, the `enter key up' event
* will still be pending in the buffer).
*/
while ((zs_read_csr(cs) & ZSRR0_RX_READY) != 0)
(void)zs_read_data(cs);
/*
* Ask the keyboard for its DIP switch settings. This will also let
* us know whether the keyboard is connected.
*/
sc->sc_dc->expected = 2;
zskbd_ctrl(cs, ZSKBD_CTRL_A_RCB, 0, 0, 0);
while (sc->sc_dc->expected != 0) {
rc = zskbd_poll(cs, &key);
if (rc != 0) {
if (rc == ENXIO && sc->sc_dc->expected == 2) {
printf("no keyboard");
/*
* Attach wskbd nevertheless, in case the
* keyboard is plugged late.
*/
sc->sc_dc->expected = 0;
goto dip;
} else {
printf("i/o error\n");
return;
}
}
zskbd_process(cs, key);
}
printf("dip switches %02x", sc->sc_dc->dip);
dip:
/*
* Disable key click by default. Note that if the keyboard is not
* currently connected, the bit will nevertheless stick and will
* disable the click as soon as a keyboard led needs to be lit.
*/
zskbd_ctrl(cs, ZSKBD_CTRL_A_NOCLICK, 0, 0, 0);
splx(s);
printf("\n");
if (zskbd_is_console)
sc->sc_dc->enabled = 1;
/* attach wskbd */
wskaa.console = zskbd_is_console;
wskaa.keymap = &sgikbd_wskbd_keymapdata;
wskaa.accessops = &zskbd_wskbd_accessops;
wskaa.accesscookie = cs;
sc->sc_dc->wskbddev = config_found(self, &wskaa, wskbddevprint);
}
void
zstty_rxsoft(struct zstty_softc *zst, struct tty *tp)
{
struct zs_chanstate *cs = zst->zst_cs;
int (*rint)(int, struct tty *) = linesw[tp->t_line].l_rint;
uint8_t *get, *end;
u_int cc, scc;
uint8_t rr1;
int code;
int s;
end = zst->zst_ebuf;
get = zst->zst_rbget;
scc = cc = zstty_rbuf_size - zst->zst_rbavail;
if (cc == zstty_rbuf_size) {
zst->zst_floods++;
if (zst->zst_errors++ == 0)
timeout_add_sec(&zst->zst_diag_ch, 60);
}
/* If not yet open, drop the entire buffer content here */
if (!ISSET(tp->t_state, TS_ISOPEN)) {
get += cc << 1;
if (get >= end)
get -= zstty_rbuf_size << 1;
cc = 0;
}
while (cc) {
code = get[0];
rr1 = get[1];
if (ISSET(rr1, ZSRR1_DO | ZSRR1_FE | ZSRR1_PE)) {
if (ISSET(rr1, ZSRR1_DO)) {
zst->zst_overflows++;
if (zst->zst_errors++ == 0)
timeout_add_sec(&zst->zst_diag_ch, 60);
}
if (ISSET(rr1, ZSRR1_FE))
SET(code, TTY_FE);
if (ISSET(rr1, ZSRR1_PE))
SET(code, TTY_PE);
}
if ((*rint)(code, tp) == -1) {
/*
* The line discipline's buffer is out of space.
*/
if (!ISSET(zst->zst_rx_flags, RX_TTY_BLOCKED)) {
/*
* We're either not using flow control, or the
* line discipline didn't tell us to block for
* some reason. Either way, we have no way to
* know when there's more space available, so
* just drop the rest of the data.
*/
get += cc << 1;
if (get >= end)
get -= zstty_rbuf_size << 1;
cc = 0;
} else {
/*
* Don't schedule any more receive processing
* until the line discipline tells us there's
* space available (through comhwiflow()).
* Leave the rest of the data in the input
* buffer.
*/
SET(zst->zst_rx_flags, RX_TTY_OVERFLOWED);
}
break;
}
get += 2;
if (get >= end)
get = zst->zst_rbuf;
cc--;
}
if (cc != scc) {
zst->zst_rbget = get;
s = splzs();
cc = zst->zst_rbavail += scc - cc;
/* Buffers should be ok again, release possible block. */
if (cc >= zst->zst_r_lowat) {
if (ISSET(zst->zst_rx_flags, RX_IBUF_OVERFLOWED)) {
CLR(zst->zst_rx_flags, RX_IBUF_OVERFLOWED);
SET(cs->cs_preg[1], ZSWR1_RIE);
cs->cs_creg[1] = cs->cs_preg[1];
zs_write_reg(cs, 1, cs->cs_creg[1]);
}
if (ISSET(zst->zst_rx_flags, RX_IBUF_BLOCKED)) {
CLR(zst->zst_rx_flags, RX_IBUF_BLOCKED);
zs_hwiflow(zst);
}
}
splx(s);
}
}
void
zs_sbdio_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct sbdio_attach_args *sa = aux;
struct zsc_attach_args zsc_args;
struct zschan *zc;
struct zs_chanstate *cs;
struct zsdevice *zs_addr;
int s, channel;
zsc->zsc_dev = self;
aprint_normal("\n");
zs_addr = (void *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1);
zsc->zsc_flags = sa->sa_flags;
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = 0;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
if (channel == 0)
zc = &zs_addr->zs_chan_a;
else
zc = &zs_addr->zs_chan_b;
if (zc == zs_consaddr) {
memcpy(cs, zs_conscs, sizeof(struct zs_chanstate));
zs_conscs = cs;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
} else {
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_defspeed = ZS_DEFSPEED;
zsc_args.hwflags = 0;
}
zs_lock_init(cs);
cs->cs_brg_clk = PCLK / 16;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
zsc->zsc_si = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
intr_establish(sa->sa_irq, zshard, zsc);
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
void
zstty_attach(struct device *parent, struct device *self, void *aux)
{
struct zsc_softc *zsc = (struct zsc_softc *)parent;
struct zstty_softc *zst = (struct zstty_softc *)self;
struct cfdata *cf = self->dv_cfdata;
struct zsc_attach_args *args = aux;
struct zs_chanstate *cs;
struct tty *tp;
int channel, s, tty_unit;
dev_t dev;
const char *i, *o;
int dtr_on;
int resetbit;
timeout_set(&zst->zst_diag_ch, zstty_diag, zst);
tty_unit = zst->zst_dev.dv_unit;
channel = args->channel;
cs = zsc->zsc_cs[channel];
cs->cs_private = zst;
cs->cs_ops = &zsops_tty;
zst->zst_cs = cs;
zst->zst_swflags = cf->cf_flags; /* softcar, etc. */
zst->zst_hwflags = args->hwflags;
dev = makedev(zs_major, tty_unit);
if (zst->zst_swflags)
printf(" flags 0x%x", zst->zst_swflags);
if (ISSET(zst->zst_hwflags, ZS_HWFLAG_NO_DCD))
SET(zst->zst_swflags, TIOCFLAG_SOFTCAR);
/*
* Check whether we serve as a console device.
* XXX - split console input/output channels aren't
* supported yet on /dev/console
*/
i = o = NULL;
if ((zst->zst_hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
i = " input";
if ((args->hwflags & ZS_HWFLAG_USE_CONSDEV) != 0) {
args->consdev->cn_dev = dev;
cn_tab->cn_pollc = args->consdev->cn_pollc;
cn_tab->cn_getc = args->consdev->cn_getc;
}
cn_tab->cn_dev = dev;
}
if ((zst->zst_hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
o = " output";
if ((args->hwflags & ZS_HWFLAG_USE_CONSDEV) != 0) {
cn_tab->cn_putc = args->consdev->cn_putc;
}
cn_tab->cn_dev = dev;
}
if (i != NULL || o != NULL) {
printf(": console%s", i ? (o ? "" : i) : o);
}
#ifdef KGDB
if (zs_check_kgdb(cs, dev)) {
/*
* Allow kgdb to "take over" this port. Returns true
* if this serial port is in-use by kgdb.
*/
printf(": kgdb\n");
/*
* This is the kgdb port (exclusive use)
* so skip the normal attach code.
*/
return;
}
#endif
#if defined(__sparc__) || defined(__sparc64__)
if (strcmp(args->type, "keyboard") == 0 ||
strcmp(args->type, "mouse") == 0)
printf(": %s", args->type);
#endif
printf("\n");
tp = ttymalloc(0);
tp->t_dev = dev;
tp->t_oproc = zsstart;
tp->t_param = zsparam;
tp->t_hwiflow = zshwiflow;
zst->zst_tty = tp;
zst->zst_rbuf = mallocarray(zstty_rbuf_size, 2, M_DEVBUF, M_WAITOK);
zst->zst_ebuf = zst->zst_rbuf + (zstty_rbuf_size * 2);
/* Disable the high water mark. */
zst->zst_r_hiwat = 0;
zst->zst_r_lowat = 0;
zst->zst_rbget = zst->zst_rbput = zst->zst_rbuf;
zst->zst_rbavail = zstty_rbuf_size;
/* if there are no enable/disable functions, assume the device
is always enabled */
if (!cs->enable)
cs->enabled = 1;
/*
* Hardware init
*/
dtr_on = 0;
resetbit = 0;
if (ISSET(zst->zst_hwflags, ZS_HWFLAG_CONSOLE)) {
/* Call zsparam similar to open. */
struct termios t;
/* Wait a while for previous console output to complete */
DELAY(10000);
/* Setup the "new" parameters in t. */
t.c_ispeed = 0;
t.c_ospeed = cs->cs_defspeed;
t.c_cflag = cs->cs_defcflag;
s = splzs();
/*
* Turn on receiver and status interrupts.
* We defer the actual write of the register to zsparam(),
* but we must make sure status interrupts are turned on by
* the time zsparam() reads the initial rr0 state.
*/
SET(cs->cs_preg[1], ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE);
splx(s);
/* Make sure zsparam will see changes. */
tp->t_ospeed = 0;
(void)zsparam(tp, &t);
/* Make sure DTR is on now. */
dtr_on = 1;
} else if (!ISSET(zst->zst_hwflags, ZS_HWFLAG_NORESET)) {
/* Not the console; may need reset. */
resetbit = (channel == 0) ? ZSWR9_A_RESET : ZSWR9_B_RESET;
}
s = splzs();
if (resetbit)
zs_write_reg(cs, 9, resetbit);
zs_modem(zst, dtr_on);
splx(s);
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
void
zsc_attach(struct device *parent, struct device *self, void *aux)
{
struct zsc_softc *zsc = (void *)self;
struct confargs *ca = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct xzs_chanstate *xcs;
struct zs_chanstate *cs;
struct zsdevice *zsd;
int zsc_unit, channel;
int s, theflags;
int node, intr[3][3];
u_int regs[16];
zsc_unit = zsc->zsc_dev.dv_unit;
zsd = mapiodev(ca->ca_baseaddr + ca->ca_reg[0], ca->ca_reg[1]);
node = OF_child(ca->ca_node); /* ch-a */
for (channel = 0; channel < 2; channel++) {
if (OF_getprop(node, "AAPL,interrupts",
intr[channel], sizeof(intr[0])) == -1 &&
OF_getprop(node, "interrupts",
intr[channel], sizeof(intr[0])) == -1) {
printf(": cannot find interrupt property\n");
return;
}
if (OF_getprop(node, "reg", regs, sizeof(regs)) < 24) {
printf(": cannot find reg property\n");
return;
}
regs[2] += ca->ca_baseaddr;
regs[4] += ca->ca_baseaddr;
#ifdef ZS_TXDMA
zsc->zsc_txdmareg[channel] = mapiodev(regs[2], regs[3]);
zsc->zsc_txdmacmd[channel] =
dbdma_alloc(sizeof(dbdma_command_t) * 3);
memset(zsc->zsc_txdmacmd[channel], 0,
sizeof(dbdma_command_t) * 3);
dbdma_reset(zsc->zsc_txdmareg[channel]);
#endif
node = OF_peer(node); /* ch-b */
}
printf(": irq %d,%d\n", intr[0][0], intr[1][0]);
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = zs_hwflags[zsc_unit][channel];
xcs = &zsc->xzsc_xcs_store[channel];
cs = &xcs->xzs_cs;
zsc->zsc_cs[channel] = cs;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
/* Current BAUD rate generator clock. */
/* RTxC is 230400*16, so use 230400 */
cs->cs_brg_clk = PCLK / 16;
if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
cs->cs_defspeed = zs_get_speed(cs);
else
cs->cs_defspeed =
zs_defspeed[zsc_unit][channel];
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR;
cs->cs_wr5_rts = 0;
#ifdef __notyet__
cs->cs_slave_type = ZS_SLAVE_NONE;
#endif
/* Define BAUD rate stuff. */
xcs->cs_clocks[0].clk = PCLK;
xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV;
xcs->cs_clocks[1].flags =
ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN;
xcs->cs_clocks[2].flags = ZSC_TRXDIV | ZSC_VARIABLE;
xcs->cs_clock_count = 3;
if (channel == 0) {
theflags = 0; /*mac68k_machine.modem_flags;*/
/*xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk;*/
/*xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk;*/
xcs->cs_clocks[1].clk = 0;
xcs->cs_clocks[2].clk = 0;
} else {
theflags = 0; /*mac68k_machine.print_flags;*/
xcs->cs_clocks[1].flags = ZSC_VARIABLE;
/*
* Yes, we aren't defining ANY clock source enables for the
* printer's DCD clock in. The hardware won't let us
* use it. But a clock will freak out the chip, so we
* let you set it, telling us to bar interrupts on the line.
*/
/*xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk;*/
/*xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk;*/
xcs->cs_clocks[1].clk = 0;
xcs->cs_clocks[2].clk = 0;
}
if (xcs->cs_clocks[1].clk)
zsc_args.hwflags |= ZS_HWFLAG_NO_DCD;
if (xcs->cs_clocks[2].clk)
zsc_args.hwflags |= ZS_HWFLAG_NO_CTS;
/* Set defaults in our "extended" chanstate. */
xcs->cs_csource = 0;
xcs->cs_psource = 0;
xcs->cs_cclk_flag = 0; /* Nothing fancy by default */
xcs->cs_pclk_flag = 0;
if (theflags & ZSMAC_RAW) {
zsc_args.hwflags |= ZS_HWFLAG_RAW;
printf(" (raw defaults)");
}
/*
* XXX - This might be better done with a "stub" driver
* (to replace zstty) that ignores LocalTalk for now.
*/
if (theflags & ZSMAC_LOCALTALK) {
printf(" shielding from LocalTalk");
cs->cs_defspeed = 1;
cs->cs_creg[ZSRR_BAUDLO] = cs->cs_preg[ZSRR_BAUDLO] = 0xff;
cs->cs_creg[ZSRR_BAUDHI] = cs->cs_preg[ZSRR_BAUDHI] = 0xff;
zs_write_reg(cs, ZSRR_BAUDLO, 0xff);
zs_write_reg(cs, ZSRR_BAUDHI, 0xff);
/*
* If we might have LocalTalk, then make sure we have the
* Baud rate low-enough to not do any damage.
*/
}
/*
* We used to disable chip interrupts here, but we now
* do that in zscnprobe, just in case MacOS left the chip on.
*/
xcs->cs_chip = 0;
/* Stash away a copy of the final H/W flags. */
xcs->cs_hwflags = zsc_args.hwflags;
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zsc_print)) {
/* No sub-driver. Just reset it. */
u_char reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/* XXX - Now safe to install interrupt handlers. */
mac_intr_establish(parent, intr[0][0], IST_LEVEL, IPL_TTY,
zshard, NULL, "zs0");
mac_intr_establish(parent, intr[1][0], IST_LEVEL, IPL_TTY,
zshard, NULL, "zs1");
#ifdef ZS_TXDMA
mac_intr_establish(parent, intr[0][1], IST_LEVEL, IPL_TTY,
zs_txdma_int, (void *)0, "zsdma0");
mac_intr_establish(parent, intr[1][1], IST_LEVEL, IPL_TTY,
zs_txdma_int, (void *)1, "zsdma1");
#endif
zsc->zsc_softintr = softintr_establish(IPL_SOFTTTY, zssoft, zsc);
if (zsc->zsc_softintr == NULL)
panic("zsattach: could not establish soft interrupt");
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splzs();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
/* connect power management for port 0 */
cs->enable = zs_enable;
cs->disable = zs_disable;
}
/*
* Attach a found zs.
*
* Match slave number to zs unit number, so that misconfiguration will
* not set up the keyboard as ttya, etc.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct confargs *ca = aux;
struct zsc_attach_args zsc_args;
struct zs_chanstate *cs;
struct zs_channel *ch;
int zs_unit, channel, s;
zsc->zsc_dev = self;
zsc->zsc_bustag = ca->ca_bustag;
if (bus_space_map(ca->ca_bustag, ca->ca_addr,
sizeof(struct zsdevice),
BUS_SPACE_MAP_LINEAR,
&zsc->zsc_base) != 0) {
aprint_error(": cannot map registers\n");
return;
}
zs_unit = device_unit(self);
aprint_normal("\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
zsc_args.hwflags = zs_hwflags[zs_unit][channel];
ch = &zsc->zsc_cs_store[channel];
cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
zs_lock_init(cs);
cs->cs_reg_csr = NULL;
cs->cs_reg_data = NULL;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base,
zs_chan_offset[channel],
sizeof(struct zschan),
&ch->cs_regs) != 0) {
aprint_error_dev(self, ": cannot map regs\n");
return;
}
ch->cs_bustag = ca->ca_bustag;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
cs->cs_defspeed = zs_get_speed(cs);
else
cs->cs_defspeed = zs_defspeed;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
zs_write_reg(cs, 9, 0);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL);
evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
