/** * zynq_slcr_get_ocm_config - Get SLCR OCM config * * return: OCM config bits */ u32 zynq_slcr_get_ocm_config(void) { u32 ret; zynq_slcr_read(&ret, SLCR_OCM_CFG_OFFSET); return ret; }
/** * zynq_slcr_cpu_stop - Stop cpu * @cpu: cpu number */ void zynq_slcr_cpu_stop(int cpu) { u32 reg; zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); }
/** * zynq_slcr_get_device_id - Read device code id * * Return: Device code id */ u32 zynq_slcr_get_device_id(void) { u32 val; zynq_slcr_read(&val, SLCR_PSS_IDCODE); val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; val &= SLCR_PSS_IDCODE_DEVICE_MASK; return val; }
/** * zynq_slcr_cpu_start - Start cpu * @cpu: cpu number */ void zynq_slcr_cpu_start(int cpu) { u32 reg; zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(SLCR_A9_CPU_RST << cpu); zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); }
void zynq_cpu_stop(cyg_uint32 cpu) { cyg_uint32 reg; zynq_slcr_unlock(); reg = zynq_slcr_read(XSLCR_A9_CPU_RST_CTRL_OFFSET); reg |= (XSLCR_A9_CPU_STOP | XSLCR_A9_CPU_RST) << cpu; zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg); zynq_slcr_lock(); }
static void zynq_cpu_start(cyg_uint32 cpu) { cyg_uint32 reg; zynq_slcr_unlock(); reg = zynq_slcr_read(XSLCR_A9_CPU_RST_CTRL_OFFSET); reg &= ~(XSLCR_A9_CPU_RST << cpu); zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg); reg &= ~(XSLCR_A9_CPU_STOP << cpu); zynq_slcr_write(XSLCR_A9_CPU_RST_CTRL_OFFSET, reg); zynq_slcr_lock(); }
/** * zynq_slcr_system_restart - Restart the entire system. * * @nb: Pointer to restart notifier block (unused) * @action: Reboot mode (unused) * @data: Restart handler private data (unused) * * Return: 0 always */ static int zynq_slcr_system_restart(struct notifier_block *nb, unsigned long action, void *data) { u32 reboot; /* * Clear 0x0F000000 bits of reboot status register to workaround * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); return 0; }
/** * zynq_slcr_system_reset - Reset the entire system. */ void zynq_slcr_system_reset(void) { u32 reboot; /* * Unlock the SLCR then reset the system. * Note that this seems to require raw i/o * functions or there's a lockup? */ zynq_slcr_unlock(); /* * Clear 0x0F000000 bits of reboot status register to workaround * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); }
/** * zynq_slcr_get_ocm_config - Get SLCR OCM config * * return: OCM config bits */ u32 zynq_slcr_get_ocm_config(void) { return zynq_slcr_read(SLCR_OCM_CFG_OFFSET); }