int board_late_init(void)
{
u32 reg = 0;
u8 bootmode;
u32 ver = zynqmp_get_silicon_version();
switch (ver) {
case ZYNQMP_CSU_VERSION_VELOCE:
setenv("setup", "setenv baudrate 4800 && setenv bootcmd run veloce");
case ZYNQMP_CSU_VERSION_EP108:
case ZYNQMP_CSU_VERSION_SILICON:
setenv("setup", "setenv serverip 10.10.70.101 && setenv ipaddr 10.10.70.1 && setenv partid auto");
break;
case ZYNQMP_CSU_VERSION_QEMU:
default:
setenv("setup", "setenv serverip 10.0.2.2 && setenv ipaddr 10.0.2.15 && setenv partid 0");
}
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
puts("Bootmode: ");
switch (bootmode) {
case JTAG_MODE:
puts("JTAG_MODE\n");
setenv("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
setenv("modeboot", "qspiboot");
puts("QSPI_MODE\n");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE:
puts("SD_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE1:
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
setenv("sdbootdev", "1");
#endif
setenv("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
setenv("modeboot", "nandboot");
break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
return 0;
}
unsigned long get_uart_clk(int dev_id)
{
u32 ver = zynqmp_get_silicon_version();
switch (ver) {
case ZYNQMP_CSU_VERSION_VELOCE:
return 48000;
case ZYNQMP_CSU_VERSION_EP108:
return 25000000;
case ZYNQMP_CSU_VERSION_QEMU:
return 133000000;
}
return 100000000;
}
int board_mmc_init(bd_t *bd)
{
int ret = 0;
u32 ver = zynqmp_get_silicon_version();
if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
}
return ret;
}
