BOOLEAN
STATIC
MemConstructRemoteNBBlockHY (
IN OUT MEM_NB_BLOCK *NBPtr,
IN DIE_STRUCT *MCTPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr
)
{
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
NBPtr->MCTPtr = MCTPtr;
NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
MemNInitNBDataHy (NBPtr);
FeatPtr->InitCPG (NBPtr);
NBPtr->FeatPtr = FeatPtr;
FeatPtr->InitHwRxEn (NBPtr);
MemNSwitchDCTNb (NBPtr, 0);
//----------------------------------------------------------------------------
// Get TSC rate of the this AP
//----------------------------------------------------------------------------
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
return TRUE;
}
/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
IDS_CALLOUT_STRUCT IdsCalloutData;
AGESA_STATUS Status;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->Version = IDS_PERF_VERSION;
IdsCalloutData.IdsNvPtr = NULL;
IdsCalloutData.StdHeader = *StdHeader;
IdsCalloutData.Reserved = 0;
Status = AgesaGetIdsData (IDS_CALLOUT_GET_PERF_BUFFER, &IdsCalloutData);
//Check if Platform BIOS provide a buffer to copy
if ((Status == AGESA_SUCCESS) && (IdsCalloutData.Reserved != 0)) {
LibAmdMemCopy ((VOID *)IdsCalloutData.Reserved, LocateHeapStructPtr.BufferPtr, sizeof (TP_Perf_STRUCT), StdHeader);
} else {
//No platform performance buffer provide, use the default HDTOUT output
if (AmdIdsHdtOutSupport () == FALSE) {
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR2_REG, 0x99cc);
LibAmdWriteCpuReg (DR7_REG, 0x02000420);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
}
}
return status;
}
VOID
MemFS3Wait10ns (
IN UINT32 Count,
IN OUT MEM_DATA_STRUCT *MemPtr
)
{
UINT32 TscRate;
UINT64 TargetTsc;
UINT64 CurrentTsc;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
ASSERT (Count <= 1000000);
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader);
LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
TargetTsc = CurrentTsc + ((Count * TscRate + 99) / 100);
do {
LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
} while (CurrentTsc < TargetTsc);
}
/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR0_REG, 0x8899);
LibAmdWriteCpuReg (DR7_REG, 0x00020402);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
return status;
}
/**
*
*
* This function is the main memory configuration function for DR DDR3
*
* Requirements:
*
* Run-Time Requirements:
* 1. Complete Hypertransport Bus Configuration
* 2. AmdMemInitDataStructDef must be run to set default values
* 3. MSR bit to allow access to high PCI regs set on all nodes
* 4. BSP in Big Real Mode
* 5. Stack available
* 6. MCG_CTL=-1, MC4_EN=0 for all CPUs
* 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
* 8. All var MTRRs reset to zero
* 9. State of NB_CFG.DisDatMsk set properly on all CPUs
*
* @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
*
* @return AGESA_STATUS
* - AGESA_ALERT
* - AGESA_FATAL
* - AGESA_SUCCESS
* - AGESA_WARNING
*/
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
)
{
MEM_SHARED_DATA mmSharedData;
MEM_MAIN_DATA_BLOCK mmData;
MEM_NB_BLOCK *NBPtr;
MEM_TECH_BLOCK *TechPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
AGESA_STATUS Retval;
UINT8 i;
UINT8 Die;
UINT8 DieCount;
UINT8 Tab;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
ASSERT (MemPtr != NULL);
AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader);
IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo);
IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping);
IDS_HDT_CONSOLE (MEM_FLOW, "\tLimitBelow1TB : %d\n", MemPtr->ParameterListPtr->LimitMemoryToBelow1Tb);
IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode);
IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue);
IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv);
IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv);
IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv);
IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature);
IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown);
IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl);
IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity);
IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle);
IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr);
IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode);
IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize);
IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl);
IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n", MemPtr->ParameterListPtr->SaveMemContextCtl);
IDS_HDT_CONSOLE (MEM_FLOW, "\tExternalVrefCtl : %d\n", MemPtr->ParameterListPtr->ExternalVrefCtl );
IDS_HDT_CONSOLE (MEM_FLOW, "\tForceTrainMode : %d\n\n", MemPtr->ParameterListPtr->ForceTrainMode );
//----------------------------------------------------------------------------
// Get TSC rate, which will be used later in Wait10ns routine
//----------------------------------------------------------------------------
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader);
//----------------------------------------------------------------------------
// Read In SPD Data
//----------------------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader);
MemSPDDataProcess (MemPtr);
//----------------------------------------------------------------
// Initialize Main Data Block
//----------------------------------------------------------------
mmData.MemPtr = MemPtr;
mmData.mmSharedPtr = &mmSharedData;
LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader);
mmSharedData.DimmExcludeFlag = NORMAL;
mmSharedData.NodeIntlv.IsValid = FALSE;
//----------------------------------------------------------------
// Discover populated CPUs
//
//----------------------------------------------------------------
Retval = MemSocketScan (&mmData);
if (Retval == AGESA_FATAL) {
return Retval;
}
DieCount = mmData.DieCount;
//----------------------------------------------------------------
//
// Allocate Memory for NB and Tech Blocks
//
// NBPtr[Die]----+
// |
// V
// +---+---+---+---+---+---+---+---+
// | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks
// +---+---+---+---+---+---+---+---+
// | | | | | | | |
// | | | | | | | |
// v v v v v v v v
// +---+---+---+---+---+---+---+---+
// | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks
// +---+---+---+---+---+---+---+---+
//
//
//----------------------------------------------------------------
AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK)));
AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
ASSERT(FALSE); // NB and Tech Block Heap allocate error
return AGESA_FATAL;
}
NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]);
mmData.NBPtr = NBPtr;
mmData.TechPtr = TechPtr;
//----------------------------------------------------------------
// Create NB Blocks
//
//----------------------------------------------------------------
for (Die = 0 ; Die < DieCount ; Die++ ) {
i = 0;
while (memNBInstalled[i].MemConstructNBBlock != 0) {
if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) {
break;
}
i++;
}
// Couldn't find a NB which supported this family
if (memNBInstalled[i].MemConstructNBBlock == 0) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Create Technology Blocks
//
//----------------------------------------------------------------
for (Die = 0 ; Die < DieCount ; Die++ ) {
i = 0;
while (memTechInstalled[i] != NULL) {
if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) {
NBPtr[Die].TechPtr = &TechPtr[Die];
break;
}
i++;
}
// Couldn't find a Tech block which supported this family
if (memTechInstalled[i] == NULL) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
//
// MEMORY INITIALIZATION TASKS
//
//----------------------------------------------------------------
i = 0;
while (memFlowControlInstalled[i] != NULL) {
Retval = memFlowControlInstalled[i] (&mmData);
if (MemPtr->IsFlowControlSupported == TRUE) {
break;
}
i++;
}
//----------------------------------------------------------------
// Deallocate NB register tables
//----------------------------------------------------------------
for (Tab = 0; Tab < NumberOfNbRegTables; Tab++) {
HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_NB_REG_TABLE, Tab, 0, 0), &MemPtr->StdHeader);
}
//----------------------------------------------------------------
// Check for errors and return
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader);
for (Die = 0; Die < DieCount; Die++) {
if (NBPtr[Die].MCTPtr->ErrCode > Retval) {
Retval = NBPtr[Die].MCTPtr->ErrCode;
}
}
return Retval;
}
/**
*
*
* This function initialize needed data structures for S3 resume.
*
* @param[in, out] **S3NBPtr - Pointer to the pointer of northbridge block.
* @param[in, out] *MemPtr - Pointer to MEM_DATA_STRUCT.
* @param[in, out] *mmData - Pointer to MEM_MAIN_DATA_BLOCK.
* @param[in] *StdHeader - Config handle for library and services.
*
* @return AGESA_STATUS
* - AGESA_ALERT
* - AGESA_FATAL
* - AGESA_SUCCESS
* - AGESA_WARNING
*/
AGESA_STATUS
MemS3InitNB (
IN OUT S3_MEM_NB_BLOCK **S3NBPtr,
IN OUT MEM_DATA_STRUCT **MemPtr,
IN OUT MEM_MAIN_DATA_BLOCK *mmData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
AGESA_STATUS RetVal;
LOCATE_HEAP_PTR LocHeap;
MEM_NB_BLOCK *NBPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
UINT8 Die;
UINT8 DieCount;
BOOLEAN SkipScan;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
SkipScan = FALSE;
LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE;
if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
// NB block has already been constructed by main block.
// No need to construct it here.
*MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr;
SkipScan = TRUE;
} else {
AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT
return AGESA_FATAL;
}
*MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(*MemPtr)->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &(*MemPtr)->TscRate, &(*MemPtr)->StdHeader);
}
mmData->MemPtr = *MemPtr;
if (!SkipScan) {
RetVal = MemSocketScan (mmData);
if (RetVal == AGESA_FATAL) {
return RetVal;
}
} else {
// We already have initialize data block, no need to do it again.
mmData->DieCount = mmData->MemPtr->DieCount;
}
DieCount = mmData->DieCount;
//---------------------------------------------
// Creation of NB Block for S3 resume
//---------------------------------------------
// Search for AMD_MEM_AUTO_HANDLE on the heap first.
// Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
// NB block has already been constructed by main block.
// No need to construct it here.
*S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
} else {
AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK)));
AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK"
return AGESA_FATAL;
}
*S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
// NB block has already been constructed by main block.
// No need to construct it here.
NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
} else {
AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK"
return AGESA_FATAL;
}
NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
}
// Construct each die.
for (Die = 0; Die < DieCount; Die ++) {
i = 0;
((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die];
while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) {
if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) {
break;
}
i++;
};
if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
ASSERT(FALSE); // S3 resume NB constructor not found
return AGESA_FATAL;
}
}
}
return AGESA_SUCCESS;
}