void BRDITEMS_PLOTTER::PlotDrillMarks()
{
/* If small drills marks were requested prepare a clamp value to pass
to the helper function */
int small_drill = (GetDrillMarksType() == PCB_PLOT_PARAMS::SMALL_DRILL_SHAPE) ?
SMALL_DRILL : 0;
/* In the filled trace mode drill marks are drawn white-on-black to scrape
the underlying pad. This works only for drivers supporting color change,
obviously... it means that:
- PS, SVG and PDF output is correct (i.e. you have a 'donut' pad)
- In HPGL you can't see them
- In gerbers you can't see them, too. This is arguably the right thing to
do since having drill marks and high speed drill stations is a sure
recipe for broken tools and angry manufacturers. If you *really* want them
you could start a layer with negative polarity to scrape the film.
- In DXF they go into the 'WHITE' layer. This could be useful.
*/
if( GetMode() == FILLED )
m_plotter->SetColor( WHITE );
for( TRACK *pts = m_board->m_Track; pts != NULL; pts = pts->Next() )
{
const VIA* via = dyn_cast<const VIA*>( pts );
if( via )
plotOneDrillMark( PAD_DRILL_CIRCLE, via->GetStart(),
wxSize( via->GetDrillValue(), 0 ),
wxSize( via->GetWidth(), 0 ), 0, small_drill );
}
for( MODULE *Module = m_board->m_Modules; Module != NULL; Module = Module->Next() )
{
for( D_PAD *pad = Module->Pads(); pad != NULL; pad = pad->Next() )
{
if( pad->GetDrillSize().x == 0 )
continue;
plotOneDrillMark( pad->GetDrillShape(),
pad->GetPosition(), pad->GetDrillSize(),
pad->GetSize(), pad->GetOrientation(),
small_drill );
}
}
if( GetMode() == FILLED )
m_plotter->SetColor( GetColor() );
}
void D_PAD::ImportSettingsFromMaster( const D_PAD& aMasterPad )
{
SetShape( aMasterPad.GetShape() );
SetLayerSet( aMasterPad.GetLayerSet() );
SetAttribute( aMasterPad.GetAttribute() );
// The pad orientation, for historical reasons is the
// pad rotation + parent rotation.
// So we have to manage this parent rotation
double pad_rot = aMasterPad.GetOrientation();
if( aMasterPad.GetParent() )
pad_rot -= aMasterPad.GetParent()->GetOrientation();
if( GetParent() )
pad_rot += GetParent()->GetOrientation();
SetOrientation( pad_rot );
SetSize( aMasterPad.GetSize() );
SetDelta( wxSize( 0, 0 ) );
SetOffset( aMasterPad.GetOffset() );
SetDrillSize( aMasterPad.GetDrillSize() );
SetDrillShape( aMasterPad.GetDrillShape() );
SetRoundRectRadiusRatio( aMasterPad.GetRoundRectRadiusRatio() );
switch( aMasterPad.GetShape() )
{
case PAD_SHAPE_TRAPEZOID:
SetDelta( aMasterPad.GetDelta() );
break;
case PAD_SHAPE_CIRCLE:
// ensure size.y == size.x
SetSize( wxSize( GetSize().x, GetSize().x ) );
break;
default:
;
}
switch( aMasterPad.GetAttribute() )
{
case PAD_ATTRIB_SMD:
case PAD_ATTRIB_CONN:
// These pads do not have hole (they are expected to be only on one
// external copper layer)
SetDrillSize( wxSize( 0, 0 ) );
break;
default:
;
}
// Add or remove custom pad shapes:
SetPrimitives( aMasterPad.GetPrimitives() );
SetAnchorPadShape( aMasterPad.GetAnchorPadShape() );
MergePrimitivesAsPolygon();
}
void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer,
SHAPE_POLY_SET& aCornerBuffer, int aInflateValue, int aMaxError,
bool aSkipNPTHPadsWihNoCopper ) const
{
D_PAD* pad = PadsList();
wxSize margin;
for( ; pad != NULL; pad = pad->Next() )
{
if( aLayer != UNDEFINED_LAYER && !pad->IsOnLayer(aLayer) )
continue;
// NPTH pads are not drawn on layers if the shape size and pos is the same
// as their hole:
if( aSkipNPTHPadsWihNoCopper && pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED )
{
if( pad->GetDrillSize() == pad->GetSize() && pad->GetOffset() == wxPoint( 0, 0 ) )
{
switch( pad->GetShape() )
{
case PAD_SHAPE_CIRCLE:
if( pad->GetDrillShape() == PAD_DRILL_SHAPE_CIRCLE )
continue;
break;
case PAD_SHAPE_OVAL:
if( pad->GetDrillShape() != PAD_DRILL_SHAPE_CIRCLE )
continue;
break;
default:
break;
}
}
}
switch( aLayer )
{
case F_Mask:
case B_Mask:
margin.x = margin.y = pad->GetSolderMaskMargin() + aInflateValue;
break;
case F_Paste:
case B_Paste:
margin = pad->GetSolderPasteMargin();
margin.x += aInflateValue;
margin.y += aInflateValue;
break;
default:
margin.x = margin.y = aInflateValue;
break;
}
pad->BuildPadShapePolygon( aCornerBuffer, margin );
}
}
/* Extract the D356 record from the modules (pads) */
static void build_pad_testpoints( BOARD *aPcb,
std::vector <D356_RECORD>& aRecords )
{
wxPoint origin = aPcb->GetAuxOrigin();
for( MODULE *module = aPcb->m_Modules;
module; module = module->Next() )
{
for( D_PAD *pad = module->Pads(); pad; pad = pad->Next() )
{
D356_RECORD rk;
rk.access = compute_pad_access_code( aPcb, pad->GetLayerSet() );
// It could be a mask only pad, we only handle pads with copper here
if( rk.access != -1 )
{
rk.netname = pad->GetNetname();
rk.refdes = module->GetReference();
pad->StringPadName( rk.pin );
rk.midpoint = false; // XXX MAYBE need to be computed (how?)
const wxSize& drill = pad->GetDrillSize();
rk.drill = std::min( drill.x, drill.y );
rk.hole = (rk.drill != 0);
rk.smd = pad->GetAttribute() == PAD_ATTRIB_SMD;
rk.mechanical = (pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED);
rk.x_location = pad->GetPosition().x - origin.x;
rk.y_location = origin.y - pad->GetPosition().y;
rk.x_size = pad->GetSize().x;
// Rule: round pads have y = 0
if( pad->GetShape() == PAD_SHAPE_CIRCLE )
rk.y_size = 0;
else
rk.y_size = pad->GetSize().y;
rk.rotation = -KiROUND( pad->GetOrientation() ) / 10;
if( rk.rotation < 0 ) rk.rotation += 360;
// the value indicates which sides are *not* accessible
rk.soldermask = 3;
if( pad->GetLayerSet()[F_Mask] )
rk.soldermask &= ~1;
if( pad->GetLayerSet()[B_Mask] )
rk.soldermask &= ~2;
aRecords.push_back( rk );
}
}
}
}
void DIALOG_PAD_PROPERTIES::PadPropertiesAccept( wxCommandEvent& event )
{
if( !padValuesOK() )
return;
bool rastnestIsChanged = false;
int isign = m_isFlipped ? -1 : 1;
transferDataToPad( m_padMaster );
// m_padMaster is a pattern: ensure there is no net for this pad:
m_padMaster->SetNetCode( NETINFO_LIST::UNCONNECTED );
if( m_currentPad ) // Set current Pad parameters
{
wxSize size;
MODULE* module = m_currentPad->GetParent();
m_parent->SaveCopyInUndoList( module, UR_CHANGED );
module->SetLastEditTime();
// redraw the area where the pad was, without pad (delete pad on screen)
m_currentPad->SetFlags( DO_NOT_DRAW );
m_parent->GetCanvas()->RefreshDrawingRect( m_currentPad->GetBoundingBox() );
m_currentPad->ClearFlags( DO_NOT_DRAW );
// Update values
m_currentPad->SetShape( m_padMaster->GetShape() );
m_currentPad->SetAttribute( m_padMaster->GetAttribute() );
if( m_currentPad->GetPosition() != m_padMaster->GetPosition() )
{
m_currentPad->SetPosition( m_padMaster->GetPosition() );
rastnestIsChanged = true;
}
// compute the pos 0 value, i.e. pad position for module with orientation = 0
// i.e. relative to module origin (module position)
wxPoint pt = m_currentPad->GetPosition() - module->GetPosition();
RotatePoint( &pt, -module->GetOrientation() );
m_currentPad->SetPos0( pt );
m_currentPad->SetOrientation( m_padMaster->GetOrientation() * isign + module->GetOrientation() );
m_currentPad->SetSize( m_padMaster->GetSize() );
size = m_padMaster->GetDelta();
size.y *= isign;
m_currentPad->SetDelta( size );
m_currentPad->SetDrillSize( m_padMaster->GetDrillSize() );
m_currentPad->SetDrillShape( m_padMaster->GetDrillShape() );
wxPoint offset = m_padMaster->GetOffset();
offset.y *= isign;
m_currentPad->SetOffset( offset );
m_currentPad->SetPadToDieLength( m_padMaster->GetPadToDieLength() );
if( m_currentPad->GetLayerSet() != m_padMaster->GetLayerSet() )
{
rastnestIsChanged = true;
m_currentPad->SetLayerSet( m_padMaster->GetLayerSet() );
}
if( m_isFlipped )
m_currentPad->SetLayerSet( FlipLayerMask( m_currentPad->GetLayerSet() ) );
m_currentPad->SetPadName( m_padMaster->GetPadName() );
wxString padNetname;
// For PAD_HOLE_NOT_PLATED, ensure there is no net name selected
if( m_padMaster->GetAttribute() != PAD_HOLE_NOT_PLATED )
padNetname = m_PadNetNameCtrl->GetValue();
if( m_currentPad->GetNetname() != padNetname )
{
const NETINFO_ITEM* netinfo = m_board->FindNet( padNetname );
if( !padNetname.IsEmpty() && netinfo == NULL )
{
DisplayError( NULL, _( "Unknown netname, netname not changed" ) );
}
else
{
rastnestIsChanged = true;
m_currentPad->SetNetCode( netinfo->GetNet() );
}
}
m_currentPad->SetLocalClearance( m_padMaster->GetLocalClearance() );
m_currentPad->SetLocalSolderMaskMargin( m_padMaster->GetLocalSolderMaskMargin() );
m_currentPad->SetLocalSolderPasteMargin( m_padMaster->GetLocalSolderPasteMargin() );
m_currentPad->SetLocalSolderPasteMarginRatio( m_padMaster->GetLocalSolderPasteMarginRatio() );
m_currentPad->SetZoneConnection( m_padMaster->GetZoneConnection() );
m_currentPad->SetThermalWidth( m_padMaster->GetThermalWidth() );
m_currentPad->SetThermalGap( m_padMaster->GetThermalGap() );
module->CalculateBoundingBox();
m_parent->SetMsgPanel( m_currentPad );
// redraw the area where the pad was
m_parent->GetCanvas()->RefreshDrawingRect( m_currentPad->GetBoundingBox() );
m_parent->OnModify();
}
EndModal( wxID_OK );
if( rastnestIsChanged ) // The net ratsnest must be recalculated
m_board->m_Status_Pcb = 0;
}
// test if all values are acceptable for the pad
bool DIALOG_PAD_PROPERTIES::padValuesOK()
{
bool error = transferDataToPad( m_dummyPad );
wxArrayString error_msgs;
wxString msg;
// Test for incorrect values
if( (m_dummyPad->GetSize().x < m_dummyPad->GetDrillSize().x) ||
(m_dummyPad->GetSize().y < m_dummyPad->GetDrillSize().y) )
{
error_msgs.Add( _( "Incorrect value for pad drill: pad drill bigger than pad size" ) );
}
LSET padlayers_mask = m_dummyPad->GetLayerSet();
if( padlayers_mask == 0 )
error_msgs.Add( _( "Error: pad has no layer" ) );
if( !padlayers_mask[F_Cu] && !padlayers_mask[B_Cu] )
{
if( m_dummyPad->GetDrillSize().x || m_dummyPad->GetDrillSize().y )
{
// Note: he message is shown in an HTML window
msg = _( "Error: the pad is not on a copper layer and has a hole" );
if( m_dummyPad->GetAttribute() == PAD_HOLE_NOT_PLATED )
{
msg += wxT("<br><br><i>");
msg += _( "For NPTH pad, set pad size value to pad drill value,"
" if you do not want this pad plotted in gerber files"
);
}
error_msgs.Add( msg );
}
}
wxPoint max_size;
max_size.x = std::abs( m_dummyPad->GetOffset().x );
max_size.y = std::abs( m_dummyPad->GetOffset().y );
max_size.x += m_dummyPad->GetDrillSize().x / 2;
max_size.y += m_dummyPad->GetDrillSize().y / 2;
if( ( m_dummyPad->GetSize().x / 2 < max_size.x ) ||
( m_dummyPad->GetSize().y / 2 < max_size.y ) )
{
error_msgs.Add( _( "Incorrect value for pad offset" ) );
}
if( error )
{
error_msgs.Add( _( "Too large value for pad delta size" ) );
}
switch( m_dummyPad->GetAttribute() )
{
case PAD_HOLE_NOT_PLATED: // Not plated, but through hole, a hole is expected
case PAD_STANDARD : // Pad through hole, a hole is also expected
if( m_dummyPad->GetDrillSize().x <= 0 )
error_msgs.Add( _( "Error: Through hole pad: drill diameter set to 0" ) );
break;
case PAD_CONN: // Connector pads are smd pads, just they do not have solder paste.
if( padlayers_mask[B_Paste] || padlayers_mask[F_Paste] )
error_msgs.Add( _( "Error: Connector pads are not on the solder paste layer\n"
"Use SMD pads instead" ) );
// Fall trough
case PAD_SMD: // SMD and Connector pads (One external copper layer only)
/*
if( padlayers_mask[B_Cu] && padlayers_mask[F_Cu] )
error_msgs.Add( _( "Error: only one copper layer allowed for SMD or Connector pads" ) );
*/
break;
}
if( error_msgs.GetCount() )
{
HTML_MESSAGE_BOX dlg( this, _("Pad setup errors list" ) );
dlg.ListSet( error_msgs );
dlg.ShowModal();
}
return error_msgs.GetCount() == 0;
}
void DIALOG_PAD_PROPERTIES::initValues()
{
wxString msg;
double angle;
// Disable pad net name wxTextCtrl if the caller is the footprint editor
// because nets are living only in the board managed by the board editor
m_canEditNetName = m_parent->IsType( FRAME_PCB );
// Setup layers names from board
// Should be made first, before calling m_rbCopperLayersSel->SetSelection()
m_rbCopperLayersSel->SetString( 0, m_board->GetLayerName( F_Cu ) );
m_rbCopperLayersSel->SetString( 1, m_board->GetLayerName( B_Cu ) );
m_PadLayerAdhCmp->SetLabel( m_board->GetLayerName( F_Adhes ) );
m_PadLayerAdhCu->SetLabel( m_board->GetLayerName( B_Adhes ) );
m_PadLayerPateCmp->SetLabel( m_board->GetLayerName( F_Paste ) );
m_PadLayerPateCu->SetLabel( m_board->GetLayerName( B_Paste ) );
m_PadLayerSilkCmp->SetLabel( m_board->GetLayerName( F_SilkS ) );
m_PadLayerSilkCu->SetLabel( m_board->GetLayerName( B_SilkS ) );
m_PadLayerMaskCmp->SetLabel( m_board->GetLayerName( F_Mask ) );
m_PadLayerMaskCu->SetLabel( m_board->GetLayerName( B_Mask ) );
m_PadLayerECO1->SetLabel( m_board->GetLayerName( Eco1_User ) );
m_PadLayerECO2->SetLabel( m_board->GetLayerName( Eco2_User ) );
m_PadLayerDraft->SetLabel( m_board->GetLayerName( Dwgs_User ) );
m_isFlipped = false;
if( m_currentPad )
{
MODULE* module = m_currentPad->GetParent();
if( module->GetLayer() == B_Cu )
{
m_isFlipped = true;
m_staticModuleSideValue->SetLabel( _( "Back side (footprint is mirrored)" ) );
}
msg.Printf( wxT( "%.1f" ), module->GetOrientation() / 10.0 );
m_staticModuleRotValue->SetLabel( msg );
}
if( m_isFlipped )
{
wxPoint pt = m_dummyPad->GetOffset();
NEGATE( pt.y );
m_dummyPad->SetOffset( pt );
wxSize sz = m_dummyPad->GetDelta();
NEGATE( sz.y );
m_dummyPad->SetDelta( sz );
// flip pad's layers
m_dummyPad->SetLayerSet( FlipLayerMask( m_dummyPad->GetLayerSet() ) );
}
m_staticTextWarningPadFlipped->Show(m_isFlipped);
m_PadNumCtrl->SetValue( m_dummyPad->GetPadName() );
m_PadNetNameCtrl->SetValue( m_dummyPad->GetNetname() );
// Display current unit name in dialog:
m_PadPosX_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadPosY_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadDrill_X_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadDrill_Y_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadShapeSizeX_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadShapeSizeY_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadShapeOffsetX_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadShapeOffsetY_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadShapeDelta_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_PadLengthDie_Unit->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
// Display current pad masks clearances units
m_NetClearanceUnits->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_SolderMaskMarginUnits->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_SolderPasteMarginUnits->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_ThermalWidthUnits->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
m_ThermalGapUnits->SetLabel( GetAbbreviatedUnitsLabel( g_UserUnit ) );
// Display current pad parameters units:
PutValueInLocalUnits( *m_PadPosition_X_Ctrl, m_dummyPad->GetPosition().x );
PutValueInLocalUnits( *m_PadPosition_Y_Ctrl, m_dummyPad->GetPosition().y );
PutValueInLocalUnits( *m_PadDrill_X_Ctrl, m_dummyPad->GetDrillSize().x );
PutValueInLocalUnits( *m_PadDrill_Y_Ctrl, m_dummyPad->GetDrillSize().y );
PutValueInLocalUnits( *m_ShapeSize_X_Ctrl, m_dummyPad->GetSize().x );
PutValueInLocalUnits( *m_ShapeSize_Y_Ctrl, m_dummyPad->GetSize().y );
PutValueInLocalUnits( *m_ShapeOffset_X_Ctrl, m_dummyPad->GetOffset().x );
PutValueInLocalUnits( *m_ShapeOffset_Y_Ctrl, m_dummyPad->GetOffset().y );
if( m_dummyPad->GetDelta().x )
{
PutValueInLocalUnits( *m_ShapeDelta_Ctrl, m_dummyPad->GetDelta().x );
m_trapDeltaDirChoice->SetSelection( 0 );
}
else
{
PutValueInLocalUnits( *m_ShapeDelta_Ctrl, m_dummyPad->GetDelta().y );
m_trapDeltaDirChoice->SetSelection( 1 );
}
PutValueInLocalUnits( *m_LengthPadToDieCtrl, m_dummyPad->GetPadToDieLength() );
PutValueInLocalUnits( *m_NetClearanceValueCtrl, m_dummyPad->GetLocalClearance() );
PutValueInLocalUnits( *m_SolderMaskMarginCtrl, m_dummyPad->GetLocalSolderMaskMargin() );
PutValueInLocalUnits( *m_ThermalWidthCtrl, m_dummyPad->GetThermalWidth() );
PutValueInLocalUnits( *m_ThermalGapCtrl, m_dummyPad->GetThermalGap() );
// These 2 parameters are usually < 0, so prepare entering a negative value, if current is 0
PutValueInLocalUnits( *m_SolderPasteMarginCtrl, m_dummyPad->GetLocalSolderPasteMargin() );
if( m_dummyPad->GetLocalSolderPasteMargin() == 0 )
m_SolderPasteMarginCtrl->SetValue( wxT( "-" ) + m_SolderPasteMarginCtrl->GetValue() );
msg.Printf( wxT( "%f" ), m_dummyPad->GetLocalSolderPasteMarginRatio() * 100.0 );
if( m_dummyPad->GetLocalSolderPasteMarginRatio() == 0.0 && msg[0] == '0' )
// Sometimes Printf adds a sign if the value is small
m_SolderPasteMarginRatioCtrl->SetValue( wxT( "-" ) + msg );
else
m_SolderPasteMarginRatioCtrl->SetValue( msg );
switch( m_dummyPad->GetZoneConnection() )
{
default:
case UNDEFINED_CONNECTION:
m_ZoneConnectionChoice->SetSelection( 0 );
break;
case PAD_IN_ZONE:
m_ZoneConnectionChoice->SetSelection( 1 );
break;
case THERMAL_PAD:
m_ZoneConnectionChoice->SetSelection( 2 );
break;
case PAD_NOT_IN_ZONE:
m_ZoneConnectionChoice->SetSelection( 3 );
break;
}
if( m_currentPad )
{
MODULE* module = m_currentPad->GetParent();
angle = m_currentPad->GetOrientation() - module->GetOrientation();
if( m_isFlipped )
NEGATE( angle );
m_dummyPad->SetOrientation( angle );
}
angle = m_dummyPad->GetOrientation();
NORMALIZE_ANGLE_180( angle ); // ? normalizing is in D_PAD::SetOrientation()
// Set layers used by this pad: :
setPadLayersList( m_dummyPad->GetLayerSet() );
// Pad Orient
switch( int( angle ) )
{
case 0:
m_PadOrient->SetSelection( 0 );
break;
case 900:
m_PadOrient->SetSelection( 1 );
break;
case -900:
m_PadOrient->SetSelection( 2 );
break;
case 1800:
case -1800:
m_PadOrient->SetSelection( 3 );
break;
default:
m_PadOrient->SetSelection( 4 );
break;
}
switch( m_dummyPad->GetShape() )
{
default:
case PAD_CIRCLE:
m_PadShape->SetSelection( 0 );
break;
case PAD_OVAL:
m_PadShape->SetSelection( 1 );
break;
case PAD_RECT:
m_PadShape->SetSelection( 2 );
break;
case PAD_TRAPEZOID:
m_PadShape->SetSelection( 3 );
break;
}
msg.Printf( wxT( "%g" ), angle );
m_PadOrientCtrl->SetValue( msg );
// Type of pad selection
m_PadType->SetSelection( 0 );
for( unsigned ii = 0; ii < DIM( code_type ); ii++ )
{
if( code_type[ii] == m_dummyPad->GetAttribute() )
{
m_PadType->SetSelection( ii );
break;
}
}
// Enable/disable Pad name,and pad length die
// (disable for NPTH pads (mechanical pads)
bool enable = m_dummyPad->GetAttribute() != PAD_HOLE_NOT_PLATED;
m_PadNumCtrl->Enable( enable );
m_PadNetNameCtrl->Enable( m_canEditNetName && enable && m_currentPad != NULL );
m_LengthPadToDieCtrl->Enable( enable );
if( m_dummyPad->GetDrillShape() != PAD_DRILL_OBLONG )
m_DrillShapeCtrl->SetSelection( 0 );
else
m_DrillShapeCtrl->SetSelection( 1 );
// Update some dialog widgets state (Enable/disable options):
wxCommandEvent cmd_event;
setPadLayersList( m_dummyPad->GetLayerSet() );
OnDrillShapeSelected( cmd_event );
OnPadShapeSelection( cmd_event );
}
static void Print_Module( EDA_DRAW_PANEL* aPanel, wxDC* aDC, MODULE* aModule,
GR_DRAWMODE aDraw_mode, LSET aMask,
PRINT_PARAMETERS::DrillShapeOptT aDrillShapeOpt )
{
// Print pads
for( D_PAD* pad = aModule->Pads(); pad; pad = pad->Next() )
{
if( !( pad->GetLayerSet() & aMask ).any() )
continue;
// Manage hole according to the print drill option
wxSize drill_tmp = pad->GetDrillSize();
switch( aDrillShapeOpt )
{
case PRINT_PARAMETERS::NO_DRILL_SHAPE:
pad->SetDrillSize( wxSize(0,0) );
break;
case PRINT_PARAMETERS::SMALL_DRILL_SHAPE:
{
wxSize sz( std::min( SMALL_DRILL, pad->GetDrillSize().x ),
std::min( SMALL_DRILL, pad->GetDrillSize().y ) );
pad->SetDrillSize( sz );
}
break;
case PRINT_PARAMETERS::FULL_DRILL_SHAPE:
// Do nothing
break;
}
pad->Draw( aPanel, aDC, aDraw_mode );
pad->SetDrillSize( drill_tmp );
}
// Print footprint graphic shapes
LSET mlayer( aModule->GetLayer() );
if( aModule->GetLayer() == B_Cu )
mlayer = LSET( B_SilkS );
else if( aModule->GetLayer() == F_Cu )
mlayer = LSET( F_SilkS );
if( ( mlayer & aMask ).any() )
{
if( aModule->Reference().IsVisible() )
aModule->Reference().Draw( aPanel, aDC, aDraw_mode );
if( aModule->Value().IsVisible() )
aModule->Value().Draw( aPanel, aDC, aDraw_mode );
}
for( EDA_ITEM* item = aModule->GraphicalItems(); item; item = item->Next() )
{
switch( item->Type() )
{
case PCB_MODULE_TEXT_T:
{
if( !( mlayer & aMask ).any() )
break;
TEXTE_MODULE* textMod = static_cast<TEXTE_MODULE*>( item );
textMod->Draw( aPanel, aDC, aDraw_mode );
break;
}
case PCB_MODULE_EDGE_T:
{
EDGE_MODULE* edge = static_cast<EDGE_MODULE*>( item );
if( !aMask[edge->GetLayer()] )
break;
edge->Draw( aPanel, aDC, aDraw_mode );
}
break;
default:
break;
}
}
}
/**
* Function AddClearanceAreasPolygonsToPolysList
* Supports a min thickness area constraint.
* Add non copper areas polygons (pads and tracks with clearance)
* to the filled copper area found
* in BuildFilledPolysListData after calculating filled areas in a zone
* Non filled copper areas are pads and track and their clearance areas
* The filled copper area must be computed just before.
* BuildFilledPolysListData() call this function just after creating the
* filled copper area polygon (without clearance areas)
* to do that this function:
* 1 - Creates the main outline (zone outline) using a correction to shrink the resulting area
* with m_ZoneMinThickness/2 value.
* The result is areas with a margin of m_ZoneMinThickness/2
* When drawing outline with segments having a thickness of m_ZoneMinThickness, the
* outlines will match exactly the initial outlines
* 3 - Add all non filled areas (pads, tracks) in group B with a clearance of m_Clearance +
* m_ZoneMinThickness/2
* in a buffer
* - If Thermal shapes are wanted, add non filled area, in order to create these thermal shapes
* 4 - calculates the polygon A - B
* 5 - put resulting list of polygons (filled areas) in m_FilledPolysList
* This zone contains pads with the same net.
* 6 - Remove insulated copper islands
* 7 - If Thermal shapes are wanted, remove unconnected stubs in thermal shapes:
* creates a buffer of polygons corresponding to stubs to remove
* sub them to the filled areas.
* Remove new insulated copper islands
*/
void ZONE_CONTAINER::AddClearanceAreasPolygonsToPolysList( BOARD* aPcb )
{
// Set the number of segments in arc approximations
if( m_ArcToSegmentsCount == ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF )
s_CircleToSegmentsCount = ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF;
else
s_CircleToSegmentsCount = ARC_APPROX_SEGMENTS_COUNT_LOW_DEF;
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* s_Correction is 1 /cos( PI/s_CircleToSegmentsCount )
*/
s_Correction = 1.0 / cos( M_PI / s_CircleToSegmentsCount );
// This KI_POLYGON_SET is the area(s) to fill, with m_ZoneMinThickness/2
KI_POLYGON_SET polyset_zone_solid_areas;
int margin = m_ZoneMinThickness / 2;
/* First, creates the main polygon (i.e. the filled area using only one outline)
* to reserve a m_ZoneMinThickness/2 margin around the outlines and holes
* this margin is the room to redraw outlines with segments having a width set to
* m_ZoneMinThickness
* so m_ZoneMinThickness is the min thickness of the filled zones areas
* the main polygon is stored in polyset_zone_solid_areas
*/
CopyPolygonsFromFilledPolysListToKiPolygonList( polyset_zone_solid_areas );
polyset_zone_solid_areas -= margin;
if( polyset_zone_solid_areas.size() == 0 )
return;
/* Calculates the clearance value that meet DRC requirements
* from m_ZoneClearance and clearance from the corresponding netclass
* We have a "local" clearance in zones because most of time
* clearance between a zone and others items is bigger than the netclass clearance
* this is more true for small clearance values
* Note also the "local" clearance is used for clearance between non copper items
* or items like texts on copper layers
*/
int zone_clearance = std::max( m_ZoneClearance, GetClearance() );
zone_clearance += margin;
/* store holes (i.e. tracks and pads areas as polygons outlines)
* in a polygon list
*/
/* items ouside the zone bounding box are skipped
* the bounding box is the zone bounding box + the biggest clearance found in Netclass list
*/
EDA_RECT item_boundingbox;
EDA_RECT zone_boundingbox = GetBoundingBox();
int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue();
biggest_clearance = std::max( biggest_clearance, zone_clearance );
zone_boundingbox.Inflate( biggest_clearance );
/*
* First : Add pads. Note: pads having the same net as zone are left in zone.
* Thermal shapes will be created later if necessary
*/
int item_clearance;
// static to avoid unnecessary memory allocation when filling many zones.
static CPOLYGONS_LIST cornerBufferPolysToSubstract;
cornerBufferPolysToSubstract.RemoveAllContours();
/* Use a dummy pad to calculate hole clerance when a pad is not on all copper layers
* and this pad has a hole
* This dummy pad has the size and shape of the hole
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( aPcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
D_PAD* nextpad;
for( D_PAD* pad = module->Pads(); pad != NULL; pad = nextpad )
{
nextpad = pad->Next(); // pad pointer can be modified by next code, so
// calculate the next pad here
if( !pad->IsOnLayer( GetLayer() ) )
{
/* Test for pads that are on top or bottom only and have a hole.
* There are curious pads but they can be used for some components that are
* inside the board (in fact inside the hole. Some photo diodes and Leds are
* like this)
*/
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
// Use a dummy pad to calculate a hole shape that have the same dimension as
// the pad hole
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetOrientation( pad->GetOrientation() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_OBLONG ?
PAD_OVAL : PAD_CIRCLE );
dummypad.SetPosition( pad->GetPosition() );
pad = &dummypad;
}
// Note: netcode <=0 means not connected item
if( ( pad->GetNetCode() != GetNetCode() ) || ( pad->GetNetCode() <= 0 ) )
{
item_clearance = pad->GetClearance() + margin;
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( item_clearance );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
pad->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
clearance,
s_CircleToSegmentsCount,
s_Correction );
}
continue;
}
if( ( GetPadConnection( pad ) == PAD_NOT_IN_ZONE )
|| ( pad->GetShape() == PAD_TRAPEZOID ) )
// PAD_TRAPEZOID shapes are not in zones because they are used in microwave apps
// and i think it is good that shapes are not changed by thermal pads or others
{
int gap = zone_clearance;
int thermalGap = GetThermalReliefGap( pad );
gap = std::max( gap, thermalGap );
item_boundingbox = pad->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
pad->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
gap,
s_CircleToSegmentsCount,
s_Correction );
}
}
}
}
/* Add holes (i.e. tracks and vias areas as polygons outlines)
* in cornerBufferPolysToSubstract
*/
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( GetLayer() ) )
continue;
if( track->GetNetCode() == GetNetCode() && (GetNetCode() != 0) )
continue;
item_clearance = track->GetClearance() + margin;
item_boundingbox = track->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
track->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
clearance,
s_CircleToSegmentsCount,
s_Correction );
}
}
/* Add module edge items that are on copper layers
* Pcbnew allows these items to be on copper layers in microwave applictions
* This is a bad thing, but must be handled here, until a better way is found
*/
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
if( !item->IsOnLayer( GetLayer() ) && !item->IsOnLayer( Edge_Cuts ) )
continue;
if( item->Type() != PCB_MODULE_EDGE_T )
continue;
item_boundingbox = item->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
( (EDGE_MODULE*) item )->TransformShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract, zone_clearance,
s_CircleToSegmentsCount, s_Correction );
}
}
}
// Add graphic items (copper texts) and board edges
for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
{
if( item->GetLayer() != GetLayer() && item->GetLayer() != Edge_Cuts )
continue;
switch( item->Type() )
{
case PCB_LINE_T:
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract,
zone_clearance, s_CircleToSegmentsCount, s_Correction );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformBoundingBoxWithClearanceToPolygon(
cornerBufferPolysToSubstract, zone_clearance );
break;
default:
break;
}
}
// Add zones outlines having an higher priority and keepout
for( int ii = 0; ii < GetBoard()->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = GetBoard()->GetArea( ii );
if( zone->GetLayer() != GetLayer() )
continue;
if( !zone->GetIsKeepout() && zone->GetPriority() <= GetPriority() )
continue;
if( zone->GetIsKeepout() && ! zone->GetDoNotAllowCopperPour() )
continue;
// A highter priority zone or keepout area is found: remove its area
item_boundingbox = zone->GetBoundingBox();
if( !item_boundingbox.Intersects( zone_boundingbox ) )
continue;
// Add the zone outline area.
// However if the zone has the same net as the current zone,
// do not add clearance.
// the zone will be connected to the current zone, but filled areas
// will use different parameters (clearance, thermal shapes )
bool addclearance = GetNetCode() != zone->GetNetCode();
int clearance = zone_clearance;
if( zone->GetIsKeepout() )
{
addclearance = true;
clearance = m_ZoneMinThickness / 2;
}
zone->TransformOutlinesShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract,
clearance, addclearance );
}
// Remove thermal symbols
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
// Rejects non-standard pads with tht-only thermal reliefs
if( GetPadConnection( pad ) == THT_THERMAL
&& pad->GetAttribute() != PAD_STANDARD )
continue;
if( GetPadConnection( pad ) != THERMAL_PAD
&& GetPadConnection( pad ) != THT_THERMAL )
continue;
if( !pad->IsOnLayer( GetLayer() ) )
continue;
if( pad->GetNetCode() != GetNetCode() )
continue;
item_boundingbox = pad->GetBoundingBox();
int thermalGap = GetThermalReliefGap( pad );
item_boundingbox.Inflate( thermalGap, thermalGap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
CreateThermalReliefPadPolygon( cornerBufferPolysToSubstract,
*pad, thermalGap,
GetThermalReliefCopperBridge( pad ),
m_ZoneMinThickness,
s_CircleToSegmentsCount,
s_Correction, s_thermalRot );
}
}
}
// cornerBufferPolysToSubstract contains polygons to substract.
// polyset_zone_solid_areas contains the main filled area
// Calculate now actual solid areas
if( cornerBufferPolysToSubstract.GetCornersCount() > 0 )
{
KI_POLYGON_SET polyset_holes;
cornerBufferPolysToSubstract.ExportTo( polyset_holes );
// Remove holes from initial area.:
polyset_zone_solid_areas -= polyset_holes;
}
// put solid areas in m_FilledPolysList:
m_FilledPolysList.RemoveAllContours();
CopyPolygonsFromKiPolygonListToFilledPolysList( polyset_zone_solid_areas );
// Remove insulated islands:
if( GetNetCode() > 0 )
TestForCopperIslandAndRemoveInsulatedIslands( aPcb );
// Now we remove all unused thermal stubs.
cornerBufferPolysToSubstract.RemoveAllContours();
// Test thermal stubs connections and add polygons to remove unconnected stubs.
// (this is a refinement for thermal relief shapes)
if( GetNetCode() > 0 )
BuildUnconnectedThermalStubsPolygonList( cornerBufferPolysToSubstract, aPcb, this,
s_Correction, s_thermalRot );
// remove copper areas corresponding to not connected stubs
if( cornerBufferPolysToSubstract.GetCornersCount() )
{
KI_POLYGON_SET polyset_holes;
cornerBufferPolysToSubstract.ExportTo( polyset_holes );
// Remove unconnected stubs
polyset_zone_solid_areas -= polyset_holes;
// put these areas in m_FilledPolysList
m_FilledPolysList.RemoveAllContours();
CopyPolygonsFromKiPolygonListToFilledPolysList( polyset_zone_solid_areas );
if( GetNetCode() > 0 )
TestForCopperIslandAndRemoveInsulatedIslands( aPcb );
}
cornerBufferPolysToSubstract.RemoveAllContours();
}
void ZONE_CONTAINER::buildFeatureHoleList( BOARD* aPcb, SHAPE_POLY_SET& aFeatures )
{
int segsPerCircle;
double correctionFactor;
// Set the number of segments in arc approximations
if( m_ArcToSegmentsCount == ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF )
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF;
else
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_LOW_DEF;
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* s_Correction is 1 /cos( PI/s_CircleToSegmentsCount )
*/
correctionFactor = 1.0 / cos( M_PI / (double) segsPerCircle );
aFeatures.RemoveAllContours();
int outline_half_thickness = m_ZoneMinThickness / 2;
int zone_clearance = std::max( m_ZoneClearance, GetClearance() );
zone_clearance += outline_half_thickness;
/* store holes (i.e. tracks and pads areas as polygons outlines)
* in a polygon list
*/
/* items ouside the zone bounding box are skipped
* the bounding box is the zone bounding box + the biggest clearance found in Netclass list
*/
EDA_RECT item_boundingbox;
EDA_RECT zone_boundingbox = GetBoundingBox();
int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue();
biggest_clearance = std::max( biggest_clearance, zone_clearance );
zone_boundingbox.Inflate( biggest_clearance );
/*
* First : Add pads. Note: pads having the same net as zone are left in zone.
* Thermal shapes will be created later if necessary
*/
int item_clearance;
/* Use a dummy pad to calculate hole clerance when a pad is not on all copper layers
* and this pad has a hole
* This dummy pad has the size and shape of the hole
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( aPcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
D_PAD* nextpad;
for( D_PAD* pad = module->Pads(); pad != NULL; pad = nextpad )
{
nextpad = pad->Next(); // pad pointer can be modified by next code, so
// calculate the next pad here
if( !pad->IsOnLayer( GetLayer() ) )
{
/* Test for pads that are on top or bottom only and have a hole.
* There are curious pads but they can be used for some components that are
* inside the board (in fact inside the hole. Some photo diodes and Leds are
* like this)
*/
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
// Use a dummy pad to calculate a hole shape that have the same dimension as
// the pad hole
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetOrientation( pad->GetOrientation() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetPosition( pad->GetPosition() );
pad = &dummypad;
}
// Note: netcode <=0 means not connected item
if( ( pad->GetNetCode() != GetNetCode() ) || ( pad->GetNetCode() <= 0 ) )
{
item_clearance = pad->GetClearance() + outline_half_thickness;
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( item_clearance );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
pad->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
continue;
}
// Pads are removed from zone if the setup is PAD_ZONE_CONN_NONE
if( GetPadConnection( pad ) == PAD_ZONE_CONN_NONE )
{
int gap = zone_clearance;
int thermalGap = GetThermalReliefGap( pad );
gap = std::max( gap, thermalGap );
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( gap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
pad->TransformShapeWithClearanceToPolygon( aFeatures,
gap,
segsPerCircle,
correctionFactor );
}
}
}
}
/* Add holes (i.e. tracks and vias areas as polygons outlines)
* in cornerBufferPolysToSubstract
*/
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( GetLayer() ) )
continue;
if( track->GetNetCode() == GetNetCode() && (GetNetCode() != 0) )
continue;
item_clearance = track->GetClearance() + outline_half_thickness;
item_boundingbox = track->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
track->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
}
/* Add module edge items that are on copper layers
* Pcbnew allows these items to be on copper layers in microwave applictions
* This is a bad thing, but must be handled here, until a better way is found
*/
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
if( !item->IsOnLayer( GetLayer() ) && !item->IsOnLayer( Edge_Cuts ) )
continue;
if( item->Type() != PCB_MODULE_EDGE_T )
continue;
item_boundingbox = item->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
( (EDGE_MODULE*) item )->TransformShapeWithClearanceToPolygon(
aFeatures, zone_clearance,
segsPerCircle, correctionFactor );
}
}
}
// Add graphic items (copper texts) and board edges
for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
{
if( item->GetLayer() != GetLayer() && item->GetLayer() != Edge_Cuts )
continue;
switch( item->Type() )
{
case PCB_LINE_T:
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
aFeatures,
zone_clearance, segsPerCircle, correctionFactor );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformBoundingBoxWithClearanceToPolygon(
aFeatures, zone_clearance );
break;
default:
break;
}
}
// Add zones outlines having an higher priority and keepout
for( int ii = 0; ii < GetBoard()->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = GetBoard()->GetArea( ii );
if( zone->GetLayer() != GetLayer() )
continue;
if( !zone->GetIsKeepout() && zone->GetPriority() <= GetPriority() )
continue;
if( zone->GetIsKeepout() && ! zone->GetDoNotAllowCopperPour() )
continue;
// A highter priority zone or keepout area is found: remove this area
item_boundingbox = zone->GetBoundingBox();
if( !item_boundingbox.Intersects( zone_boundingbox ) )
continue;
// Add the zone outline area.
// However if the zone has the same net as the current zone,
// do not add any clearance.
// the zone will be connected to the current zone, but filled areas
// will use different parameters (clearance, thermal shapes )
bool same_net = GetNetCode() == zone->GetNetCode();
bool use_net_clearance = true;
int min_clearance = zone_clearance;
// Do not forget to make room to draw the thick outlines
// of the hole created by the area of the zone to remove
int holeclearance = zone->GetClearance() + outline_half_thickness;
// The final clearance is obviously the max value of each zone clearance
min_clearance = std::max( min_clearance, holeclearance );
if( zone->GetIsKeepout() || same_net )
{
// Just take in account the fact the outline has a thickness, so
// the actual area to substract is inflated to take in account this fact
min_clearance = outline_half_thickness;
use_net_clearance = false;
}
zone->TransformOutlinesShapeWithClearanceToPolygon(
aFeatures,
min_clearance, use_net_clearance );
}
// Remove thermal symbols
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
// Rejects non-standard pads with tht-only thermal reliefs
if( GetPadConnection( pad ) == PAD_ZONE_CONN_THT_THERMAL
&& pad->GetAttribute() != PAD_ATTRIB_STANDARD )
continue;
if( GetPadConnection( pad ) != PAD_ZONE_CONN_THERMAL
&& GetPadConnection( pad ) != PAD_ZONE_CONN_THT_THERMAL )
continue;
if( !pad->IsOnLayer( GetLayer() ) )
continue;
if( pad->GetNetCode() != GetNetCode() )
continue;
item_boundingbox = pad->GetBoundingBox();
int thermalGap = GetThermalReliefGap( pad );
item_boundingbox.Inflate( thermalGap, thermalGap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
CreateThermalReliefPadPolygon( aFeatures,
*pad, thermalGap,
GetThermalReliefCopperBridge( pad ),
m_ZoneMinThickness,
segsPerCircle,
correctionFactor, s_thermalRot );
}
}
}
}
/* Plot a copper layer or mask.
* Silk screen layers are not plotted here.
*/
void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
LAYER_MSK aLayerMask, const PCB_PLOT_PARAMS& aPlotOpt )
{
BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
itemplotter.SetLayerMask( aLayerMask );
EDA_DRAW_MODE_T plotMode = aPlotOpt.GetMode();
// Plot edge layer and graphic items
itemplotter.PlotBoardGraphicItems();
// Draw footprint shapes without pads (pads will plotted later)
// We plot here module texts, but they are usually on silkscreen layer,
// so they are not plot here but plot by PlotSilkScreen()
// Plot footprints fields (ref, value ...)
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
if( ! itemplotter.PlotAllTextsModule( module ) )
{
wxLogMessage( _( "Your BOARD has a bad layer number for module %s" ),
GetChars( module->GetReference() ) );
}
}
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
if( ! (aLayerMask & GetLayerMask( item->GetLayer() ) ) )
continue;
switch( item->Type() )
{
case PCB_MODULE_EDGE_T:
itemplotter.Plot_1_EdgeModule( (EDGE_MODULE*) item );
break;
default:
break;
}
}
}
// Plot footprint pads
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
if( (pad->GetLayerMask() & aLayerMask) == 0 )
continue;
wxSize margin;
double width_adj = 0;
if( aLayerMask & ALL_CU_LAYERS )
width_adj = itemplotter.getFineWidthAdj();
switch( aLayerMask &
( SOLDERMASK_LAYER_BACK | SOLDERMASK_LAYER_FRONT |
SOLDERPASTE_LAYER_BACK | SOLDERPASTE_LAYER_FRONT ) )
{
case SOLDERMASK_LAYER_FRONT:
case SOLDERMASK_LAYER_BACK:
margin.x = margin.y = pad->GetSolderMaskMargin();
break;
case SOLDERPASTE_LAYER_FRONT:
case SOLDERPASTE_LAYER_BACK:
margin = pad->GetSolderPasteMargin();
break;
default:
break;
}
wxSize padPlotsSize;
padPlotsSize.x = pad->GetSize().x + ( 2 * margin.x ) + width_adj;
padPlotsSize.y = pad->GetSize().y + ( 2 * margin.y ) + width_adj;
// Don't draw a null size item :
if( padPlotsSize.x <= 0 || padPlotsSize.y <= 0 )
continue;
EDA_COLOR_T color = BLACK;
if( (pad->GetLayerMask() & LAYER_BACK) )
color = aBoard->GetVisibleElementColor( PAD_BK_VISIBLE );
if((pad->GetLayerMask() & LAYER_FRONT ) )
color = ColorFromInt( color | aBoard->GetVisibleElementColor( PAD_FR_VISIBLE ) );
// Temporary set the pad size to the required plot size:
wxSize tmppadsize = pad->GetSize();
pad->SetSize( padPlotsSize );
switch( pad->GetShape() )
{
case PAD_CIRCLE:
case PAD_OVAL:
if( aPlotOpt.GetSkipPlotNPTH_Pads() &&
(pad->GetSize() == pad->GetDrillSize()) &&
(pad->GetAttribute() == PAD_HOLE_NOT_PLATED) )
break;
// Fall through:
case PAD_TRAPEZOID:
case PAD_RECT:
default:
itemplotter.PlotPad( pad, color, plotMode );
break;
}
pad->SetSize( tmppadsize ); // Restore the pad size
}
}
// Plot vias on copper layers, and if aPlotOpt.GetPlotViaOnMaskLayer() is true,
// plot them on solder mask
for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
{
const VIA* Via = dynamic_cast<const VIA*>( track );
if( !Via )
continue;
// vias are not plotted if not on selected layer, but if layer
// is SOLDERMASK_LAYER_BACK or SOLDERMASK_LAYER_FRONT,vias are drawn,
// only if they are on the corresponding external copper layer
int via_mask_layer = Via->GetLayerMask();
if( aPlotOpt.GetPlotViaOnMaskLayer() )
{
if( via_mask_layer & LAYER_BACK )
via_mask_layer |= SOLDERMASK_LAYER_BACK;
if( via_mask_layer & LAYER_FRONT )
via_mask_layer |= SOLDERMASK_LAYER_FRONT;
}
if( ( via_mask_layer & aLayerMask ) == 0 )
continue;
int via_margin = 0;
double width_adj = 0;
// If the current layer is a solder mask, use the global mask
// clearance for vias
if( ( aLayerMask & ( SOLDERMASK_LAYER_BACK | SOLDERMASK_LAYER_FRONT ) ) )
via_margin = aBoard->GetDesignSettings().m_SolderMaskMargin;
if( aLayerMask & ALL_CU_LAYERS )
width_adj = itemplotter.getFineWidthAdj();
int diameter = Via->GetWidth() + 2 * via_margin + width_adj;
// Don't draw a null size item :
if( diameter <= 0 )
continue;
EDA_COLOR_T color = aBoard->GetVisibleElementColor(VIAS_VISIBLE + Via->GetViaType());
// Set plot color (change WHITE to LIGHTGRAY because
// the white items are not seen on a white paper or screen
aPlotter->SetColor( color != WHITE ? color : LIGHTGRAY);
aPlotter->FlashPadCircle( Via->GetStart(), diameter, plotMode );
}
// Plot tracks (not vias) :
for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
{
if( track->Type() == PCB_VIA_T )
continue;
if( (GetLayerMask( track->GetLayer() ) & aLayerMask) == 0 )
continue;
int width = track->GetWidth() + itemplotter.getFineWidthAdj();
aPlotter->SetColor( itemplotter.getColor( track->GetLayer() ) );
aPlotter->ThickSegment( track->GetStart(), track->GetEnd(), width, plotMode );
}
// Plot zones (outdated, for old boards compatibility):
for( TRACK* track = aBoard->m_Zone; track; track = track->Next() )
{
if( (GetLayerMask( track->GetLayer() ) & aLayerMask) == 0 )
continue;
int width = track->GetWidth() + itemplotter.getFineWidthAdj();
aPlotter->SetColor( itemplotter.getColor( track->GetLayer() ) );
aPlotter->ThickSegment( track->GetStart(), track->GetEnd(), width, plotMode );
}
// Plot filled ares
for( int ii = 0; ii < aBoard->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = aBoard->GetArea( ii );
if( ( GetLayerMask(zone->GetLayer() ) & aLayerMask ) == 0 )
continue;
itemplotter.PlotFilledAreas( zone );
}
// Adding drill marks, if required and if the plotter is able to plot them:
if( aPlotOpt.GetDrillMarksType() != PCB_PLOT_PARAMS::NO_DRILL_SHAPE )
itemplotter.PlotDrillMarks();
}
void EXCELLON_WRITER::BuildHolesList( LAYER_PAIR aLayerPair,
bool aGenerateNPTH_list )
{
HOLE_INFO new_hole;
m_holeListBuffer.clear();
m_toolListBuffer.clear();
wxASSERT( aLayerPair.first < aLayerPair.second ); // fix the caller
// build hole list for vias
if( ! aGenerateNPTH_list ) // vias are always plated !
{
for( VIA* via = GetFirstVia( m_pcb->m_Track ); via; via = GetFirstVia( via->Next() ) )
{
int hole_sz = via->GetDrillValue();
if( hole_sz == 0 ) // Should not occur.
continue;
new_hole.m_Tool_Reference = -1; // Flag value for Not initialized
new_hole.m_Hole_Orient = 0;
new_hole.m_Hole_Diameter = hole_sz;
new_hole.m_Hole_NotPlated = false;
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Pos = via->GetStart();
via->LayerPair( &new_hole.m_Hole_Top_Layer, &new_hole.m_Hole_Bottom_Layer );
// LayerPair() returns params with m_Hole_Bottom_Layer > m_Hole_Top_Layer
// Remember: top layer = 0 and bottom layer = 31 for through hole vias
// Any captured via should be from aLayerPair.first to aLayerPair.second exactly.
if( new_hole.m_Hole_Top_Layer != aLayerPair.first ||
new_hole.m_Hole_Bottom_Layer != aLayerPair.second )
continue;
m_holeListBuffer.push_back( new_hole );
}
}
if( aLayerPair == LAYER_PAIR( F_Cu, B_Cu ) )
{
// add holes for thru hole pads
for( MODULE* module = m_pcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
if( !m_merge_PTH_NPTH )
{
if( !aGenerateNPTH_list && pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED )
continue;
if( aGenerateNPTH_list && pad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED )
continue;
}
if( pad->GetDrillSize().x == 0 )
continue;
new_hole.m_Hole_NotPlated = (pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED);
new_hole.m_Tool_Reference = -1; // Flag is: Not initialized
new_hole.m_Hole_Orient = pad->GetOrientation();
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Diameter = std::min( pad->GetDrillSize().x, pad->GetDrillSize().y );
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
if( pad->GetDrillShape() != PAD_DRILL_SHAPE_CIRCLE )
new_hole.m_Hole_Shape = 1; // oval flag set
new_hole.m_Hole_Size = pad->GetDrillSize();
new_hole.m_Hole_Pos = pad->GetPosition(); // hole position
new_hole.m_Hole_Bottom_Layer = B_Cu;
new_hole.m_Hole_Top_Layer = F_Cu; // pad holes are through holes
m_holeListBuffer.push_back( new_hole );
}
}
}
// Sort holes per increasing diameter value
sort( m_holeListBuffer.begin(), m_holeListBuffer.end(), CmpHoleSettings );
// build the tool list
int last_hole = -1; // Set to not initialized (this is a value not used
// for m_holeListBuffer[ii].m_Hole_Diameter)
bool last_notplated_opt = false;
DRILL_TOOL new_tool( 0, false );
unsigned jj;
for( unsigned ii = 0; ii < m_holeListBuffer.size(); ii++ )
{
if( m_holeListBuffer[ii].m_Hole_Diameter != last_hole ||
m_holeListBuffer[ii].m_Hole_NotPlated != last_notplated_opt )
{
new_tool.m_Diameter = m_holeListBuffer[ii].m_Hole_Diameter;
new_tool.m_Hole_NotPlated = m_holeListBuffer[ii].m_Hole_NotPlated;
m_toolListBuffer.push_back( new_tool );
last_hole = new_tool.m_Diameter;
last_notplated_opt = new_tool.m_Hole_NotPlated;
}
jj = m_toolListBuffer.size();
if( jj == 0 )
continue; // Should not occurs
m_holeListBuffer[ii].m_Tool_Reference = jj; // Tool value Initialized (value >= 1)
m_toolListBuffer.back().m_TotalCount++;
if( m_holeListBuffer[ii].m_Hole_Shape )
m_toolListBuffer.back().m_OvalCount++;
}
}
void EDA_3D_CANVAS::buildBoardThroughHolesPolygonList( SHAPE_POLY_SET& allBoardHoles,
int aSegCountPerCircle, bool aOptimizeLargeCircles )
{
// hole diameter value to change seg count by circle:
int small_hole_limit = Millimeter2iu( 1.0 );
int copper_thickness = GetPrm3DVisu().GetCopperThicknessBIU();
BOARD* pcb = GetBoard();
// Build holes of through vias:
for( TRACK* track = pcb->m_Track; track; track = track->Next() )
{
if( track->Type() != PCB_VIA_T )
continue;
VIA *via = static_cast<VIA*>( track );
if( via->GetViaType() != VIA_THROUGH )
continue;
int holediameter = via->GetDrillValue();
int hole_outer_radius = (holediameter + copper_thickness) / 2;
TransformCircleToPolygon( allBoardHoles,
via->GetStart(), hole_outer_radius,
aSegCountPerCircle );
}
// Build holes of through pads:
for( MODULE* footprint = pcb->m_Modules; footprint; footprint = footprint->Next() )
{
for( D_PAD* pad = footprint->Pads(); pad; pad = pad->Next() )
{
// Calculate a factor to apply to segcount for large holes ( > 1 mm)
// (bigger pad drill size -> more segments) because holes in pads can have
// very different sizes and optimizing this segcount gives a better look
// Mainly mounting holes have a size bigger than small_hole_limit
wxSize padHole = pad->GetDrillSize();
if( ! padHole.x ) // Not drilled pad like SMD pad
continue;
// we use the hole diameter to calculate the seg count.
// for round holes, padHole.x == padHole.y
// for oblong holes, the diameter is the smaller of (padHole.x, padHole.y)
int diam = std::min( padHole.x, padHole.y );
int segcount = aSegCountPerCircle;
if( diam > small_hole_limit )
{
double segFactor = (double)diam / small_hole_limit;
segcount = (int)(aSegCountPerCircle * segFactor);
// limit segcount to 48. For a circle this is a very good approx.
if( segcount > 48 )
segcount = 48;
}
// The hole in the body is inflated by copper thickness.
int inflate = copper_thickness;
// If not plated, no copper.
if( pad->GetAttribute () == PAD_HOLE_NOT_PLATED )
inflate = 0;
pad->BuildPadDrillShapePolygon( allBoardHoles, inflate, segcount );
}
}
allBoardHoles.Simplify();
}
// test if all values are acceptable for the pad
bool DIALOG_PAD_PROPERTIES::padValuesOK()
{
bool error = transferDataToPad( m_dummyPad );
wxArrayString error_msgs;
wxString msg;
// Test for incorrect values
if( (m_dummyPad->GetSize().x < m_dummyPad->GetDrillSize().x) ||
(m_dummyPad->GetSize().y < m_dummyPad->GetDrillSize().y) )
{
error_msgs.Add( _( "Incorrect value for pad drill: pad drill bigger than pad size" ) );
}
LAYER_MSK padlayers_mask = m_dummyPad->GetLayerMask();
if( ( padlayers_mask == 0 ) && ( m_dummyPad->GetAttribute() != PAD_HOLE_NOT_PLATED ) )
error_msgs.Add( _( "Error: pad has no layer and is not a mechanical pad" ) );
padlayers_mask &= (LAYER_BACK | LAYER_FRONT);
if( padlayers_mask == 0 )
{
if( m_dummyPad->GetDrillSize().x || m_dummyPad->GetDrillSize().y )
{
msg = _( "Error: pad is not on a copper layer and has a hole" );
if( m_dummyPad->GetAttribute() == PAD_HOLE_NOT_PLATED )
{
msg += wxT("\n");
msg += _( "For NPTH pad, set pad drill value to pad size value,\n"
"if you do not want this pad plotted in gerber files"
);
}
error_msgs.Add( msg );
}
}
wxPoint max_size;
max_size.x = std::abs( m_dummyPad->GetOffset().x );
max_size.y = std::abs( m_dummyPad->GetOffset().y );
max_size.x += m_dummyPad->GetDrillSize().x / 2;
max_size.y += m_dummyPad->GetDrillSize().y / 2;
if( ( m_dummyPad->GetSize().x / 2 < max_size.x ) ||
( m_dummyPad->GetSize().y / 2 < max_size.y ) )
{
error_msgs.Add( _( "Incorrect value for pad offset" ) );
}
if( error )
{
error_msgs.Add( _( "Too large value for pad delta size" ) );
}
switch( m_dummyPad->GetAttribute() )
{
case PAD_STANDARD : // Pad through hole, a hole is expected
if( m_dummyPad->GetDrillSize().x <= 0 )
error_msgs.Add( _( "Incorrect value for pad drill (too small value)" ) );
break;
case PAD_SMD: // SMD and Connector pads (One external copper layer only)
if( (padlayers_mask & LAYER_BACK) && (padlayers_mask & LAYER_FRONT) )
error_msgs.Add( _( "Error: only one copper layer allowed for this pad" ) );
break;
case PAD_CONN: // connectors can have pads on "All" Cu layers.
break;
case PAD_HOLE_NOT_PLATED: // Not plated
break;
}
if( error_msgs.GetCount() )
{
HTML_MESSAGE_BOX dlg( this, _("Pad setup errors list" ) );
dlg.ListSet( error_msgs );
dlg.ShowModal();
}
return error_msgs.GetCount() == 0;
}
void DIALOG_PAD_PROPERTIES::OnPaintShowPanel( wxPaintEvent& event )
{
wxPaintDC dc( m_panelShowPad );
PAD_DRAWINFO drawInfo;
EDA_COLOR_T color = BLACK;
if( m_dummyPad->GetLayerSet()[F_Cu] )
{
color = m_board->GetVisibleElementColor( PAD_FR_VISIBLE );
}
if( m_dummyPad->GetLayerSet()[B_Cu] )
{
color = ColorMix( color, m_board->GetVisibleElementColor( PAD_BK_VISIBLE ) );
}
// What could happen: the pad color is *actually* black, or no
// copper was selected
if( color == BLACK )
color = LIGHTGRAY;
drawInfo.m_Color = color;
drawInfo.m_HoleColor = DARKGRAY;
drawInfo.m_Offset = m_dummyPad->GetPosition();
drawInfo.m_Display_padnum = true;
drawInfo.m_Display_netname = true;
if( m_dummyPad->GetAttribute() == PAD_HOLE_NOT_PLATED )
drawInfo.m_ShowNotPlatedHole = true;
// Shows the local pad clearance
drawInfo.m_PadClearance = m_dummyPad->GetLocalClearance();
wxSize dc_size = dc.GetSize();
dc.SetDeviceOrigin( dc_size.x / 2, dc_size.y / 2 );
// Calculate a suitable scale to fit the available draw area
int dim = m_dummyPad->GetSize().x + std::abs( m_dummyPad->GetDelta().y );
// Invalid x size. User could enter zero, or have deleted all text prior to
// entering a new value; this is also treated as zero. If dim is left at
// zero, the drawing scale is zero and we get a crash.
if( dim == 0 )
{
// If drill size has been set, use that. Otherwise default to 1mm.
dim = m_dummyPad->GetDrillSize().x;
if( dim == 0 )
dim = 1000000;
}
if( m_dummyPad->GetLocalClearance() > 0 )
dim += m_dummyPad->GetLocalClearance() * 2;
double scale = (double) dc_size.x / dim;
// If the pad is a circle, use the x size here instead.
int ysize;
if( m_dummyPad->GetShape() == PAD_CIRCLE )
ysize = m_dummyPad->GetSize().x;
else
ysize = m_dummyPad->GetSize().y;
dim = ysize + std::abs( m_dummyPad->GetDelta().x );
// Invalid y size. See note about x size above.
if( dim == 0 )
{
dim = m_dummyPad->GetDrillSize().y;
if( dim == 0 )
dim = 1000000;
}
if( m_dummyPad->GetLocalClearance() > 0 )
dim += m_dummyPad->GetLocalClearance() * 2;
double altscale = (double) dc_size.y / dim;
scale = std::min( scale, altscale );
// Give a margin
scale *= 0.7;
dc.SetUserScale( scale, scale );
GRResetPenAndBrush( &dc );
m_dummyPad->DrawShape( NULL, &dc, drawInfo );
// Draw X and Y axis.
// this is particularly useful to show the reference position of pads
// with offset and no hole
GRLine( NULL, &dc, -dim, 0, dim, 0, 0, BLUE ); // X axis
GRLine( NULL, &dc, 0, -dim, 0, dim, 0, BLUE ); // Y axis
event.Skip();
}
void ZONE_FILLER::buildZoneFeatureHoleList( const ZONE_CONTAINER* aZone,
SHAPE_POLY_SET& aFeatures ) const
{
int segsPerCircle;
double correctionFactor;
// Set the number of segments in arc approximations
if( aZone->GetArcSegmentCount() == ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF )
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF;
else
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_LOW_DEF;
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* s_Correction is 1 /cos( PI/s_CircleToSegmentsCount )
*/
correctionFactor = 1.0 / cos( M_PI / (double) segsPerCircle );
aFeatures.RemoveAllContours();
int outline_half_thickness = aZone->GetMinThickness() / 2;
// When removing holes, the holes must be expanded by outline_half_thickness
// to take in account the thickness of the zone outlines
int zone_clearance = aZone->GetClearance() + outline_half_thickness;
// When holes are created by non copper items (edge cut items), use only
// the m_ZoneClearance parameter (zone clearance with no netclass clearance)
int zone_to_edgecut_clearance = aZone->GetZoneClearance() + outline_half_thickness;
/* store holes (i.e. tracks and pads areas as polygons outlines)
* in a polygon list
*/
/* items ouside the zone bounding box are skipped
* the bounding box is the zone bounding box + the biggest clearance found in Netclass list
*/
EDA_RECT item_boundingbox;
EDA_RECT zone_boundingbox = aZone->GetBoundingBox();
int biggest_clearance = m_board->GetDesignSettings().GetBiggestClearanceValue();
biggest_clearance = std::max( biggest_clearance, zone_clearance );
zone_boundingbox.Inflate( biggest_clearance );
/*
* First : Add pads. Note: pads having the same net as zone are left in zone.
* Thermal shapes will be created later if necessary
*/
/* Use a dummy pad to calculate hole clearance when a pad is not on all copper layers
* and this pad has a hole
* This dummy pad has the size and shape of the hole
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( m_board ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
for( MODULE* module = m_board->m_Modules; module; module = module->Next() )
{
D_PAD* nextpad;
for( D_PAD* pad = module->PadsList(); pad != NULL; pad = nextpad )
{
nextpad = pad->Next(); // pad pointer can be modified by next code, so
// calculate the next pad here
if( !pad->IsOnLayer( aZone->GetLayer() ) )
{
/* Test for pads that are on top or bottom only and have a hole.
* There are curious pads but they can be used for some components that are
* inside the board (in fact inside the hole. Some photo diodes and Leds are
* like this)
*/
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
// Use a dummy pad to calculate a hole shape that have the same dimension as
// the pad hole
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetOrientation( pad->GetOrientation() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetPosition( pad->GetPosition() );
pad = &dummypad;
}
// Note: netcode <=0 means not connected item
if( ( pad->GetNetCode() != aZone->GetNetCode() ) || ( pad->GetNetCode() <= 0 ) )
{
int item_clearance = pad->GetClearance() + outline_half_thickness;
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( item_clearance );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
// PAD_SHAPE_CUSTOM can have a specific keepout, to avoid to break the shape
if( pad->GetShape() == PAD_SHAPE_CUSTOM
&& pad->GetCustomShapeInZoneOpt() == CUST_PAD_SHAPE_IN_ZONE_CONVEXHULL )
{
// the pad shape in zone can be its convex hull or
// the shape itself
SHAPE_POLY_SET outline( pad->GetCustomShapeAsPolygon() );
outline.Inflate( KiROUND( clearance * correctionFactor ), segsPerCircle );
pad->CustomShapeAsPolygonToBoardPosition( &outline,
pad->GetPosition(), pad->GetOrientation() );
if( pad->GetCustomShapeInZoneOpt() == CUST_PAD_SHAPE_IN_ZONE_CONVEXHULL )
{
std::vector<wxPoint> convex_hull;
BuildConvexHull( convex_hull, outline );
aFeatures.NewOutline();
for( unsigned ii = 0; ii < convex_hull.size(); ++ii )
aFeatures.Append( convex_hull[ii] );
}
else
aFeatures.Append( outline );
}
else
pad->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
continue;
}
// Pads are removed from zone if the setup is PAD_ZONE_CONN_NONE
// or if they have a custom shape, because a thermal relief will break
// the shape
if( aZone->GetPadConnection( pad ) == PAD_ZONE_CONN_NONE
|| pad->GetShape() == PAD_SHAPE_CUSTOM )
{
int gap = zone_clearance;
int thermalGap = aZone->GetThermalReliefGap( pad );
gap = std::max( gap, thermalGap );
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( gap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
// PAD_SHAPE_CUSTOM has a specific keepout, to avoid to break the shape
// the pad shape in zone can be its convex hull or the shape itself
if( pad->GetShape() == PAD_SHAPE_CUSTOM
&& pad->GetCustomShapeInZoneOpt() == CUST_PAD_SHAPE_IN_ZONE_CONVEXHULL )
{
// the pad shape in zone can be its convex hull or
// the shape itself
SHAPE_POLY_SET outline( pad->GetCustomShapeAsPolygon() );
outline.Inflate( KiROUND( gap * correctionFactor ), segsPerCircle );
pad->CustomShapeAsPolygonToBoardPosition( &outline,
pad->GetPosition(), pad->GetOrientation() );
std::vector<wxPoint> convex_hull;
BuildConvexHull( convex_hull, outline );
aFeatures.NewOutline();
for( unsigned ii = 0; ii < convex_hull.size(); ++ii )
aFeatures.Append( convex_hull[ii] );
}
else
pad->TransformShapeWithClearanceToPolygon( aFeatures,
gap, segsPerCircle, correctionFactor );
}
}
}
}
/* Add holes (i.e. tracks and vias areas as polygons outlines)
* in cornerBufferPolysToSubstract
*/
for( auto track : m_board->Tracks() )
{
if( !track->IsOnLayer( aZone->GetLayer() ) )
continue;
if( track->GetNetCode() == aZone->GetNetCode() && ( aZone->GetNetCode() != 0) )
continue;
int item_clearance = track->GetClearance() + outline_half_thickness;
item_boundingbox = track->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
track->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
}
/* Add module edge items that are on copper layers
* Pcbnew allows these items to be on copper layers in microwave applictions
* This is a bad thing, but must be handled here, until a better way is found
*/
for( auto module : m_board->Modules() )
{
for( auto item : module->GraphicalItems() )
{
if( !item->IsOnLayer( aZone->GetLayer() ) && !item->IsOnLayer( Edge_Cuts ) )
continue;
if( item->Type() != PCB_MODULE_EDGE_T )
continue;
item_boundingbox = item->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int zclearance = zone_clearance;
if( item->IsOnLayer( Edge_Cuts ) )
// use only the m_ZoneClearance, not the clearance using
// the netclass value, because we do not have a copper item
zclearance = zone_to_edgecut_clearance;
( (EDGE_MODULE*) item )->TransformShapeWithClearanceToPolygon(
aFeatures, zclearance, segsPerCircle, correctionFactor );
}
}
}
// Add graphic items (copper texts) and board edges
// Currently copper texts have no net, so only the zone_clearance
// is used.
for( auto item : m_board->Drawings() )
{
if( item->GetLayer() != aZone->GetLayer() && item->GetLayer() != Edge_Cuts )
continue;
int zclearance = zone_clearance;
if( item->GetLayer() == Edge_Cuts )
// use only the m_ZoneClearance, not the clearance using
// the netclass value, because we do not have a copper item
zclearance = zone_to_edgecut_clearance;
switch( item->Type() )
{
case PCB_LINE_T:
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
aFeatures,
zclearance, segsPerCircle, correctionFactor );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformBoundingBoxWithClearanceToPolygon(
aFeatures, zclearance );
break;
default:
break;
}
}
// Add zones outlines having an higher priority and keepout
for( int ii = 0; ii < m_board->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = m_board->GetArea( ii );
// If the zones share no common layers
if( !aZone->CommonLayerExists( zone->GetLayerSet() ) )
continue;
if( !zone->GetIsKeepout() && zone->GetPriority() <= aZone->GetPriority() )
continue;
if( zone->GetIsKeepout() && !zone->GetDoNotAllowCopperPour() )
continue;
// A highter priority zone or keepout area is found: remove this area
item_boundingbox = zone->GetBoundingBox();
if( !item_boundingbox.Intersects( zone_boundingbox ) )
continue;
// Add the zone outline area.
// However if the zone has the same net as the current zone,
// do not add any clearance.
// the zone will be connected to the current zone, but filled areas
// will use different parameters (clearance, thermal shapes )
bool same_net = aZone->GetNetCode() == zone->GetNetCode();
bool use_net_clearance = true;
int min_clearance = zone_clearance;
// Do not forget to make room to draw the thick outlines
// of the hole created by the area of the zone to remove
int holeclearance = zone->GetClearance() + outline_half_thickness;
// The final clearance is obviously the max value of each zone clearance
min_clearance = std::max( min_clearance, holeclearance );
if( zone->GetIsKeepout() || same_net )
{
// Just take in account the fact the outline has a thickness, so
// the actual area to substract is inflated to take in account this fact
min_clearance = outline_half_thickness;
use_net_clearance = false;
}
zone->TransformOutlinesShapeWithClearanceToPolygon(
aFeatures, min_clearance, use_net_clearance );
}
// Remove thermal symbols
for( auto module : m_board->Modules() )
{
for( auto pad : module->Pads() )
{
// Rejects non-standard pads with tht-only thermal reliefs
if( aZone->GetPadConnection( pad ) == PAD_ZONE_CONN_THT_THERMAL
&& pad->GetAttribute() != PAD_ATTRIB_STANDARD )
continue;
if( aZone->GetPadConnection( pad ) != PAD_ZONE_CONN_THERMAL
&& aZone->GetPadConnection( pad ) != PAD_ZONE_CONN_THT_THERMAL )
continue;
if( !pad->IsOnLayer( aZone->GetLayer() ) )
continue;
if( pad->GetNetCode() != aZone->GetNetCode() )
continue;
item_boundingbox = pad->GetBoundingBox();
int thermalGap = aZone->GetThermalReliefGap( pad );
item_boundingbox.Inflate( thermalGap, thermalGap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
CreateThermalReliefPadPolygon( aFeatures,
*pad, thermalGap,
aZone->GetThermalReliefCopperBridge( pad ),
aZone->GetMinThickness(),
segsPerCircle,
correctionFactor, s_thermalRot );
}
}
}
}
/*
* Function BuildHolesList
* Create the list of holes and tools for a given board
* The list is sorted by increasing drill values
* Only holes from aFirstLayer to aLastLayer copper layers are listed (for vias, because pad holes are always through holes)
* param aPcb : the given board
* param aHoleListBuffer : the std::vector<HOLE_INFO> to fill with pcb holes info
* param aToolListBuffer : the std::vector<DRILL_TOOL> to fill with tools to use
* param aFirstLayer = first layer to consider. if < 0 aFirstLayer is ignored (used to creates report file)
* param aLastLayer = last layer to consider. if < 0 aLastLayer is ignored
* param aExcludeThroughHoles : if true, exclude through holes ( pads and vias through )
* param aGenerateNPTH_list :
* true to create NPTH only list (with no plated holes)
* false to created plated holes list (with no NPTH )
*/
void Build_Holes_List( BOARD* aPcb,
std::vector<HOLE_INFO>& aHoleListBuffer,
std::vector<DRILL_TOOL>& aToolListBuffer,
int aFirstLayer, int aLastLayer, bool aExcludeThroughHoles,
bool aGenerateNPTH_list )
{
HOLE_INFO new_hole;
int hole_value;
aHoleListBuffer.clear();
aToolListBuffer.clear();
if( (aFirstLayer >= 0) && (aLastLayer >= 0) )
{
if( aFirstLayer > aLastLayer )
EXCHG( aFirstLayer, aLastLayer );
}
/* build hole list for vias
*/
if( ! aGenerateNPTH_list ) // vias are always plated !
{
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( track->Type() != PCB_VIA_T )
continue;
SEGVIA* via = (SEGVIA*) track;
hole_value = via->GetDrillValue();
if( hole_value == 0 )
continue;
new_hole.m_Tool_Reference = -1; // Flag value for Not initialized
new_hole.m_Hole_Orient = 0;
new_hole.m_Hole_Diameter = hole_value;
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Pos = via->m_Start;
via->ReturnLayerPair( &new_hole.m_Hole_Top_Layer, &new_hole.m_Hole_Bottom_Layer );
// ReturnLayerPair return params with m_Hole_Bottom_Layer < m_Hole_Top_Layer
if( (new_hole.m_Hole_Bottom_Layer > aFirstLayer) && (aFirstLayer >= 0) )
continue;
if( (new_hole.m_Hole_Top_Layer < aLastLayer) && (aLastLayer >= 0) )
continue;
if( aExcludeThroughHoles && (new_hole.m_Hole_Bottom_Layer == LAYER_N_BACK)
&& (new_hole.m_Hole_Top_Layer == LAYER_N_FRONT) )
continue;
aHoleListBuffer.push_back( new_hole );
}
}
// build hole list for pads (assumed always through holes)
if( !aExcludeThroughHoles || aGenerateNPTH_list )
{
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
// Read and analyse pads
for( D_PAD* pad = module->m_Pads; pad; pad = pad->Next() )
{
if( ! aGenerateNPTH_list && pad->GetAttribute() == PAD_HOLE_NOT_PLATED )
continue;
if( aGenerateNPTH_list && pad->GetAttribute() != PAD_HOLE_NOT_PLATED )
continue;
if( pad->GetDrillSize().x == 0 )
continue;
new_hole.m_Hole_NotPlated = (pad->GetAttribute() == PAD_HOLE_NOT_PLATED);
new_hole.m_Tool_Reference = -1; // Flag is: Not initialized
new_hole.m_Hole_Orient = pad->GetOrientation();
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Diameter = std::min( pad->GetDrillSize().x, pad->GetDrillSize().y );
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
if( pad->GetDrillShape() != PAD_CIRCLE )
new_hole.m_Hole_Shape = 1; // oval flag set
new_hole.m_Hole_Size = pad->GetDrillSize();
new_hole.m_Hole_Pos = pad->GetPosition(); // hole position
new_hole.m_Hole_Bottom_Layer = LAYER_N_BACK;
new_hole.m_Hole_Top_Layer = LAYER_N_FRONT;// pad holes are through holes
aHoleListBuffer.push_back( new_hole );
}
}
}
// Sort holes per increasing diameter value
sort( aHoleListBuffer.begin(), aHoleListBuffer.end(), CmpHoleDiameterValue );
// build the tool list
int LastHole = -1; /* Set to not initialised (this is a value not used
* for aHoleListBuffer[ii].m_Hole_Diameter) */
DRILL_TOOL new_tool( 0 );
unsigned jj;
for( unsigned ii = 0; ii < aHoleListBuffer.size(); ii++ )
{
if( aHoleListBuffer[ii].m_Hole_Diameter != LastHole )
{
new_tool.m_Diameter = ( aHoleListBuffer[ii].m_Hole_Diameter );
aToolListBuffer.push_back( new_tool );
LastHole = new_tool.m_Diameter;
}
jj = aToolListBuffer.size();
if( jj == 0 )
continue; // Should not occurs
aHoleListBuffer[ii].m_Tool_Reference = jj; // Tool value Initialized (value >= 1)
aToolListBuffer.back().m_TotalCount++;
if( aHoleListBuffer[ii].m_Hole_Shape )
aToolListBuffer.back().m_OvalCount++;
}
}
/**
* Function idf_export_module
* retrieves information from all board modules, adds drill holes to
* the DRILLED_HOLES or BOARD_OUTLINE section as appropriate,
* compiles data for the PLACEMENT section and compiles data for
* the library ELECTRICAL section.
*/
static void idf_export_module( BOARD* aPcb, MODULE* aModule,
IDF3_BOARD& aIDFBoard )
{
// Reference Designator
std::string crefdes = TO_UTF8( aModule->GetReference() );
if( crefdes.empty() || !crefdes.compare( "~" ) )
{
std::string cvalue = TO_UTF8( aModule->GetValue() );
// if both the RefDes and Value are empty or set to '~' the board owns the part,
// otherwise associated parts of the module must be marked NOREFDES.
if( cvalue.empty() || !cvalue.compare( "~" ) )
crefdes = "BOARD";
else
crefdes = "NOREFDES";
}
// TODO: If module cutouts are supported we must add code here
// for( EDA_ITEM* item = aModule->GraphicalItems(); item != NULL; item = item->Next() )
// {
// if( ( item->Type() != PCB_MODULE_EDGE_T )
// || (item->GetLayer() != Edge_Cuts ) ) continue;
// code to export cutouts
// }
// Export pads
double drill, x, y;
double scale = aIDFBoard.GetUserScale();
IDF3::KEY_PLATING kplate;
std::string pintype;
std::string tstr;
double dx, dy;
aIDFBoard.GetUserOffset( dx, dy );
for( D_PAD* pad = aModule->Pads(); pad; pad = pad->Next() )
{
drill = (double) pad->GetDrillSize().x * scale;
x = pad->GetPosition().x * scale + dx;
y = -pad->GetPosition().y * scale + dy;
// Export the hole on the edge layer
if( drill > 0.0 )
{
// plating
if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED )
kplate = IDF3::NPTH;
else
kplate = IDF3::PTH;
// hole type
tstr = TO_UTF8( pad->GetPadName() );
if( tstr.empty() || !tstr.compare( "0" ) || !tstr.compare( "~" )
|| ( kplate == IDF3::NPTH )
||( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ) )
pintype = "MTG";
else
pintype = "PIN";
// fields:
// 1. hole dia. : float
// 2. X coord : float
// 3. Y coord : float
// 4. plating : PTH | NPTH
// 5. Assoc. part : BOARD | NOREFDES | PANEL | {"refdes"}
// 6. type : PIN | VIA | MTG | TOOL | { "other" }
// 7. owner : MCAD | ECAD | UNOWNED
if( ( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG )
&& ( pad->GetDrillSize().x != pad->GetDrillSize().y ) )
{
// NOTE: IDF does not have direct support for slots;
// slots are implemented as a board cutout and we
// cannot represent plating or reference designators
double dlength = pad->GetDrillSize().y * scale;
// NOTE: The orientation of modules and pads have
// the opposite sense due to KiCad drawing on a
// screen with a LH coordinate system
double angle = pad->GetOrientation() / 10.0;
// NOTE: Since this code assumes the scenario where
// GetDrillSize().y is the length but idf_parser.cpp
// assumes a length along the X axis, the orientation
// must be shifted +90 deg when GetDrillSize().y is
// the major axis.
if( dlength < drill )
{
std::swap( drill, dlength );
}
else
{
angle += 90.0;
}
// NOTE: KiCad measures a slot's length from end to end
// rather than between the centers of the arcs
dlength -= drill;
aIDFBoard.AddSlot( drill, dlength, angle, x, y );
}
else
{
IDF_DRILL_DATA *dp = new IDF_DRILL_DATA( drill, x, y, kplate, crefdes,
pintype, IDF3::ECAD );
if( !aIDFBoard.AddDrill( dp ) )
{
delete dp;
std::ostringstream ostr;
ostr << __FILE__ << ":" << __LINE__ << ":" << __FUNCTION__;
ostr << "(): could not add drill";
throw std::runtime_error( ostr.str() );
}
}
}
}
// add any valid models to the library item list
std::string refdes;
IDF3_COMPONENT* comp = NULL;
for( S3D_MASTER* modfile = aModule->Models(); modfile != 0; modfile = modfile->Next() )
{
if( !modfile->Is3DType( S3D_MASTER::FILE3D_IDF )
|| modfile->GetShape3DFullFilename().empty() )
continue;
if( refdes.empty() )
{
refdes = TO_UTF8( aModule->GetReference() );
// NOREFDES cannot be used or else the software gets confused
// when writing out the placement data due to conflicting
// placement and layer specifications; to work around this we
// create a (hopefully) unique refdes for our exported part.
if( refdes.empty() || !refdes.compare( "~" ) )
refdes = aIDFBoard.GetNewRefDes();
}
IDF3_COMP_OUTLINE* outline;
outline = aIDFBoard.GetComponentOutline( modfile->GetShape3DFullFilename() );
if( !outline )
throw( std::runtime_error( aIDFBoard.GetError() ) );
double rotz = aModule->GetOrientation()/10.0;
double locx = modfile->m_MatPosition.x * 25.4; // part offsets are in inches
double locy = modfile->m_MatPosition.y * 25.4;
double locz = modfile->m_MatPosition.z * 25.4;
double lrot = modfile->m_MatRotation.z;
bool top = ( aModule->GetLayer() == B_Cu ) ? false : true;
if( top )
{
locy = -locy;
RotatePoint( &locx, &locy, aModule->GetOrientation() );
locy = -locy;
}
if( !top )
{
lrot = -lrot;
RotatePoint( &locx, &locy, aModule->GetOrientation() );
locy = -locy;
rotz = 180.0 - rotz;
if( rotz >= 360.0 )
while( rotz >= 360.0 ) rotz -= 360.0;
if( rotz <= -360.0 )
while( rotz <= -360.0 ) rotz += 360.0;
}
if( comp == NULL )
comp = aIDFBoard.FindComponent( refdes );
if( comp == NULL )
{
comp = new IDF3_COMPONENT( &aIDFBoard );
if( comp == NULL )
throw( std::runtime_error( aIDFBoard.GetError() ) );
comp->SetRefDes( refdes );
if( top )
comp->SetPosition( aModule->GetPosition().x * scale + dx,
-aModule->GetPosition().y * scale + dy,
rotz, IDF3::LYR_TOP );
else
comp->SetPosition( aModule->GetPosition().x * scale + dx,
-aModule->GetPosition().y * scale + dy,
rotz, IDF3::LYR_BOTTOM );
comp->SetPlacement( IDF3::PS_ECAD );
aIDFBoard.AddComponent( comp );
}
else
{
double refX, refY, refA;
IDF3::IDF_LAYER side;
if( ! comp->GetPosition( refX, refY, refA, side ) )
{
// place the item
if( top )
comp->SetPosition( aModule->GetPosition().x * scale + dx,
-aModule->GetPosition().y * scale + dy,
rotz, IDF3::LYR_TOP );
else
comp->SetPosition( aModule->GetPosition().x * scale + dx,
-aModule->GetPosition().y * scale + dy,
rotz, IDF3::LYR_BOTTOM );
comp->SetPlacement( IDF3::PS_ECAD );
}
else
{
// check that the retrieved component matches this one
refX = refX - ( aModule->GetPosition().x * scale + dx );
refY = refY - ( -aModule->GetPosition().y * scale + dy );
refA = refA - rotz;
refA *= refA;
refX *= refX;
refY *= refY;
refX += refY;
// conditions: same side, X,Y coordinates within 10 microns,
// angle within 0.01 degree
if( ( top && side == IDF3::LYR_BOTTOM ) || ( !top && side == IDF3::LYR_TOP )
|| ( refA > 0.0001 ) || ( refX > 0.0001 ) )
{
comp->GetPosition( refX, refY, refA, side );
std::ostringstream ostr;
ostr << "* " << __FILE__ << ":" << __LINE__ << ":" << __FUNCTION__ << "():\n";
ostr << "* conflicting Reference Designator '" << refdes << "'\n";
ostr << "* X loc: " << (aModule->GetPosition().x * scale + dx);
ostr << " vs. " << refX << "\n";
ostr << "* Y loc: " << (-aModule->GetPosition().y * scale + dy);
ostr << " vs. " << refY << "\n";
ostr << "* angle: " << rotz;
ostr << " vs. " << refA << "\n";
if( top )
ostr << "* TOP vs. ";
else
ostr << "* BOTTOM vs. ";
if( side == IDF3::LYR_TOP )
ostr << "TOP";
else
ostr << "BOTTOM";
throw( std::runtime_error( ostr.str() ) );
}
}
}
// create the local data ...
IDF3_COMP_OUTLINE_DATA* data = new IDF3_COMP_OUTLINE_DATA( comp, outline );
data->SetOffsets( locx, locy, locz, lrot );
comp->AddOutlineData( data );
}
return;
}
/* Plot outlines of copper, for copper layer
*/
void PlotLayerOutlines( BOARD* aBoard, PLOTTER* aPlotter,
LSET aLayerMask, const PCB_PLOT_PARAMS& aPlotOpt )
{
BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
itemplotter.SetLayerSet( aLayerMask );
SHAPE_POLY_SET outlines;
for( LSEQ seq = aLayerMask.Seq( plot_seq, DIM( plot_seq ) ); seq; ++seq )
{
LAYER_ID layer = *seq;
outlines.RemoveAllContours();
aBoard->ConvertBrdLayerToPolygonalContours( layer, outlines );
outlines.Simplify();
// Plot outlines
std::vector< wxPoint > cornerList;
// Now we have one or more basic polygons: plot each polygon
for( int ii = 0; ii < outlines.OutlineCount(); ii++ )
{
for(int kk = 0; kk <= outlines.HoleCount (ii); kk++ )
{
cornerList.clear();
const SHAPE_LINE_CHAIN& path = (kk == 0) ? outlines.COutline( ii ) : outlines.CHole( ii, kk - 1 );
for( int jj = 0; jj < path.PointCount(); jj++ )
cornerList.push_back( wxPoint( path.CPoint( jj ).x , path.CPoint( jj ).y ) );
// Ensure the polygon is closed
if( cornerList[0] != cornerList[cornerList.size() - 1] )
cornerList.push_back( cornerList[0] );
aPlotter->PlotPoly( cornerList, NO_FILL );
}
}
// Plot pad holes
if( aPlotOpt.GetDrillMarksType() != PCB_PLOT_PARAMS::NO_DRILL_SHAPE )
{
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
wxSize hole = pad->GetDrillSize();
if( hole.x == 0 || hole.y == 0 )
continue;
if( hole.x == hole.y )
aPlotter->Circle( pad->GetPosition(), hole.x, NO_FILL );
else
{
wxPoint drl_start, drl_end;
int width;
pad->GetOblongDrillGeometry( drl_start, drl_end, width );
aPlotter->ThickSegment( pad->GetPosition() + drl_start,
pad->GetPosition() + drl_end, width, SKETCH );
}
}
}
}
// Plot vias holes
for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
{
const VIA* via = dyn_cast<const VIA*>( track );
if( via && via->IsOnLayer( layer ) ) // via holes can be not through holes
{
aPlotter->Circle( via->GetPosition(), via->GetDrillValue(), NO_FILL );
}
}
}
}
void DIALOG_GENDRILL::InitDisplayParams()
{
wxString msg;
m_Choice_Unit->SetSelection( m_UnitDrillIsInch ? 1 : 0 );
m_Choice_Zeros_Format->SetSelection( m_ZerosFormat );
UpdatePrecisionOptions();
m_Check_Minimal->SetValue( m_MinimalHeader );
if( m_DrillOriginIsAuxAxis )
m_Choice_Drill_Offset->SetSelection( 1 );
m_Check_Mirror->SetValue( m_Mirror );
m_Check_Merge_PTH_NPTH->SetValue( m_Merge_PTH_NPTH );
m_Choice_Drill_Map->SetSelection( m_mapFileType );
m_ViaDrillValue->SetLabel( _( "Use Netclass values" ) );
m_MicroViaDrillValue->SetLabel( _( "Use Netclass values" ) );
// See if we have some buried vias or/and microvias, and display
// microvias drill value if so
m_throughViasCount = 0;
m_microViasCount = 0;
m_blindOrBuriedViasCount = 0;
for( TRACK* track = m_parent->GetBoard()->m_Track; track != NULL; track = track->Next() )
{
const VIA *via = dynamic_cast<const VIA*>( track );
if( via )
{
switch( via->GetViaType() )
{
case VIA_THROUGH:
m_throughViasCount++;
break;
case VIA_MICROVIA:
m_microViasCount++;
break;
case VIA_BLIND_BURIED:
m_blindOrBuriedViasCount++;
break;
default:
break;
}
}
}
m_MicroViaDrillValue->Enable( m_microViasCount );
// Count plated pad holes and not plated pad holes:
m_platedPadsHoleCount = 0;
m_notplatedPadsHoleCount = 0;
for( MODULE* module = m_parent->GetBoard()->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
if( pad->GetDrillShape() == PAD_DRILL_SHAPE_CIRCLE )
{
if( pad->GetDrillSize().x != 0 )
{
if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED )
m_notplatedPadsHoleCount++;
else
m_platedPadsHoleCount++;
}
}
else
{
if( pad->GetDrillSize().x != 0 && pad->GetDrillSize().y != 0 )
{
if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED )
m_notplatedPadsHoleCount++;
else
m_platedPadsHoleCount++;
}
}
}
}
// Display hole counts:
msg = m_PlatedPadsCountInfoMsg->GetLabel();
msg << wxT( " " ) << m_platedPadsHoleCount;
m_PlatedPadsCountInfoMsg->SetLabel( msg );
msg = m_NotPlatedPadsCountInfoMsg->GetLabel();
msg << wxT( " " ) << m_notplatedPadsHoleCount;
m_NotPlatedPadsCountInfoMsg->SetLabel( msg );
msg = m_ThroughViasInfoMsg->GetLabel();
msg << wxT( " " ) << m_throughViasCount;
m_ThroughViasInfoMsg->SetLabel( msg );
msg = m_MicroViasInfoMsg->GetLabel();
msg << wxT( " " ) << m_microViasCount;
m_MicroViasInfoMsg->SetLabel( msg );
msg = m_BuriedViasInfoMsg->GetLabel();
msg << wxT( " " ) << m_blindOrBuriedViasCount;
m_BuriedViasInfoMsg->SetLabel( msg );
// Output directory
m_outputDirectoryName->SetValue( m_plotOpts.GetOutputDirectory() );
}
// Emit PADS and PADSTACKS. They are sorted and emitted uniquely.
// Via name is synthesized from their attributes, pads are numbered
static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
{
std::vector<D_PAD*> pads;
std::vector<D_PAD*> padstacks;
std::vector<VIA*> vias;
std::vector<VIA*> viastacks;
padstacks.resize( 1 ); // We count pads from 1
// The master layermask (i.e. the enabled layers) for padstack generation
LSET master_layermask = aPcb->GetDesignSettings().GetEnabledLayers();
int cu_count = aPcb->GetCopperLayerCount();
fputs( "$PADS\n", aFile );
// Enumerate and sort the pads
if( aPcb->GetPadCount() > 0 )
{
pads = aPcb->GetPads();
qsort( &pads[0], aPcb->GetPadCount(), sizeof( D_PAD* ),
PadListSortByShape );
}
// The same for vias
for( VIA* via = GetFirstVia( aPcb->m_Track ); via;
via = GetFirstVia( via->Next() ) )
{
vias.push_back( via );
}
qsort( &vias[0], vias.size(), sizeof(VIA*), ViaSort );
// Emit vias pads
TRACK* old_via = 0;
for( unsigned i = 0; i < vias.size(); i++ )
{
VIA* via = vias[i];
if( old_via && 0 == ViaSort( &old_via, &via ) )
continue;
old_via = via;
viastacks.push_back( via );
fprintf( aFile, "PAD V%d.%d.%s ROUND %g\nCIRCLE 0 0 %g\n",
via->GetWidth(), via->GetDrillValue(),
fmt_mask( via->GetLayerSet() ).c_str(),
via->GetDrillValue() / SCALE_FACTOR,
via->GetWidth() / (SCALE_FACTOR * 2) );
}
// Emit component pads
D_PAD* old_pad = 0;
int pad_name_number = 0;
for( unsigned i = 0; i<pads.size(); ++i )
{
D_PAD* pad = pads[i];
pad->SetSubRatsnest( pad_name_number );
if( old_pad && 0==D_PAD::Compare( old_pad, pad ) )
continue; // already created
old_pad = pad;
pad_name_number++;
pad->SetSubRatsnest( pad_name_number );
fprintf( aFile, "PAD P%d", pad->GetSubRatsnest() );
padstacks.push_back( pad ); // Will have its own padstack later
int dx = pad->GetSize().x / 2;
int dy = pad->GetSize().y / 2;
switch( pad->GetShape() )
{
default:
case PAD_SHAPE_CIRCLE:
fprintf( aFile, " ROUND %g\n",
pad->GetDrillSize().x / SCALE_FACTOR );
/* Circle is center, radius */
fprintf( aFile, "CIRCLE %g %g %g\n",
pad->GetOffset().x / SCALE_FACTOR,
-pad->GetOffset().y / SCALE_FACTOR,
pad->GetSize().x / (SCALE_FACTOR * 2) );
break;
case PAD_SHAPE_RECT:
fprintf( aFile, " RECTANGULAR %g\n",
pad->GetDrillSize().x / SCALE_FACTOR );
// Rectangle is begin, size *not* begin, end!
fprintf( aFile, "RECTANGLE %g %g %g %g\n",
(-dx + pad->GetOffset().x ) / SCALE_FACTOR,
(-dy - pad->GetOffset().y ) / SCALE_FACTOR,
dx / (SCALE_FACTOR / 2), dy / (SCALE_FACTOR / 2) );
break;
case PAD_SHAPE_OVAL: // Create outline by 2 lines and 2 arcs
{
// OrCAD Layout call them OVAL or OBLONG - GenCAD call them FINGERs
fprintf( aFile, " FINGER %g\n",
pad->GetDrillSize().x / SCALE_FACTOR );
int dr = dx - dy;
if( dr >= 0 ) // Horizontal oval
{
int radius = dy;
fprintf( aFile, "LINE %g %g %g %g\n",
(-dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - radius) / SCALE_FACTOR,
(dr + pad->GetOffset().x ) / SCALE_FACTOR,
(-pad->GetOffset().y - radius) / SCALE_FACTOR );
// GenCAD arcs are (start, end, center)
fprintf( aFile, "ARC %g %g %g %g %g %g\n",
(dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - radius) / SCALE_FACTOR,
(dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y + radius) / SCALE_FACTOR,
(dr + pad->GetOffset().x) / SCALE_FACTOR,
-pad->GetOffset().y / SCALE_FACTOR );
fprintf( aFile, "LINE %g %g %g %g\n",
(dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y + radius) / SCALE_FACTOR,
(-dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y + radius) / SCALE_FACTOR );
fprintf( aFile, "ARC %g %g %g %g %g %g\n",
(-dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y + radius) / SCALE_FACTOR,
(-dr + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - radius) / SCALE_FACTOR,
(-dr + pad->GetOffset().x) / SCALE_FACTOR,
-pad->GetOffset().y / SCALE_FACTOR );
}
else // Vertical oval
{
dr = -dr;
int radius = dx;
fprintf( aFile, "LINE %g %g %g %g\n",
(-radius + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - dr) / SCALE_FACTOR,
(-radius + pad->GetOffset().x ) / SCALE_FACTOR,
(-pad->GetOffset().y + dr) / SCALE_FACTOR );
fprintf( aFile, "ARC %g %g %g %g %g %g\n",
(-radius + pad->GetOffset().x ) / SCALE_FACTOR,
(-pad->GetOffset().y + dr) / SCALE_FACTOR,
(radius + pad->GetOffset().x ) / SCALE_FACTOR,
(-pad->GetOffset().y + dr) / SCALE_FACTOR,
pad->GetOffset().x / SCALE_FACTOR,
(-pad->GetOffset().y + dr) / SCALE_FACTOR );
fprintf( aFile, "LINE %g %g %g %g\n",
(radius + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y + dr) / SCALE_FACTOR,
(radius + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - dr) / SCALE_FACTOR );
fprintf( aFile, "ARC %g %g %g %g %g %g\n",
(radius + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - dr) / SCALE_FACTOR,
(-radius + pad->GetOffset().x) / SCALE_FACTOR,
(-pad->GetOffset().y - dr) / SCALE_FACTOR,
pad->GetOffset().x / SCALE_FACTOR,
(-pad->GetOffset().y - dr) / SCALE_FACTOR );
}
}
break;
case PAD_SHAPE_TRAPEZOID:
fprintf( aFile, " POLYGON %g\n",
pad->GetDrillSize().x / SCALE_FACTOR );
// XXX TO BE IMPLEMENTED! and I don't know if it could be actually imported by something
break;
}
}
fputs( "\n$ENDPADS\n\n", aFile );
// Now emit the padstacks definitions, using the combined layer masks
fputs( "$PADSTACKS\n", aFile );
// Via padstacks
for( unsigned i = 0; i < viastacks.size(); i++ )
{
VIA* via = viastacks[i];
LSET mask = via->GetLayerSet() & master_layermask;
fprintf( aFile, "PADSTACK VIA%d.%d.%s %g\n",
via->GetWidth(), via->GetDrillValue(),
fmt_mask( mask ).c_str(),
via->GetDrillValue() / SCALE_FACTOR );
for( LSEQ seq = mask.Seq( gc_seq, DIM( gc_seq ) ); seq; ++seq )
{
LAYER_ID layer = *seq;
fprintf( aFile, "PAD V%d.%d.%s %s 0 0\n",
via->GetWidth(), via->GetDrillValue(),
fmt_mask( mask ).c_str(),
GenCADLayerName( cu_count, layer ).c_str()
);
}
}
/* Component padstacks
* CAM350 don't apply correctly the FLIP semantics for padstacks, i.e. doesn't
* swap the top and bottom layers... so I need to define the shape as MIRRORX
* and define a separate 'flipped' padstack... until it appears yet another
* noncompliant importer */
for( unsigned i = 1; i < padstacks.size(); i++ )
{
D_PAD* pad = padstacks[i];
// Straight padstack
fprintf( aFile, "PADSTACK PAD%u %g\n", i, pad->GetDrillSize().x / SCALE_FACTOR );
LSET pad_set = pad->GetLayerSet() & master_layermask;
// the special gc_seq
for( LSEQ seq = pad_set.Seq( gc_seq, DIM( gc_seq ) ); seq; ++seq )
{
LAYER_ID layer = *seq;
fprintf( aFile, "PAD P%u %s 0 0\n", i, GenCADLayerName( cu_count, layer ).c_str() );
}
// Flipped padstack
fprintf( aFile, "PADSTACK PAD%uF %g\n", i, pad->GetDrillSize().x / SCALE_FACTOR );
// the normal LAYER_ID sequence is inverted from gc_seq[]
for( LSEQ seq = pad_set.Seq(); seq; ++seq )
{
LAYER_ID layer = *seq;
fprintf( aFile, "PAD P%u %s 0 0\n", i, GenCADLayerNameFlipped( cu_count, layer ).c_str() );
}
}
fputs( "$ENDPADSTACKS\n\n", aFile );
}
void EXCELLON_WRITER::BuildHolesList( int aFirstLayer,
int aLastLayer,
bool aExcludeThroughHoles,
bool aGenerateNPTH_list,
bool aMerge_PTH_NPTH )
{
HOLE_INFO new_hole;
int hole_value;
m_holeListBuffer.clear();
m_toolListBuffer.clear();
if( (aFirstLayer >= 0) && (aLastLayer >= 0) )
{
if( aFirstLayer > aLastLayer )
std::swap( aFirstLayer, aLastLayer );
}
if ( aGenerateNPTH_list && aMerge_PTH_NPTH )
{
return;
}
// build hole list for vias
if( ! aGenerateNPTH_list ) // vias are always plated !
{
for( VIA* via = GetFirstVia( m_pcb->m_Track ); via; via = GetFirstVia( via->Next() ) )
{
hole_value = via->GetDrillValue();
if( hole_value == 0 ) // Should not occur.
continue;
new_hole.m_Tool_Reference = -1; // Flag value for Not initialized
new_hole.m_Hole_Orient = 0;
new_hole.m_Hole_Diameter = hole_value;
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Pos = via->GetStart();
via->LayerPair( &new_hole.m_Hole_Top_Layer, &new_hole.m_Hole_Bottom_Layer );
// LayerPair return params with m_Hole_Bottom_Layer > m_Hole_Top_Layer
// Remember: top layer = 0 and bottom layer = 31 for through hole vias
// the via should be at least from aFirstLayer to aLastLayer
if( (new_hole.m_Hole_Top_Layer > aFirstLayer) && (aFirstLayer >= 0) )
continue; // via above the first layer
if( (new_hole.m_Hole_Bottom_Layer < aLastLayer) && (aLastLayer >= 0) )
continue; // via below the last layer
if( aExcludeThroughHoles && (new_hole.m_Hole_Bottom_Layer == B_Cu)
&& (new_hole.m_Hole_Top_Layer == F_Cu) )
continue;
m_holeListBuffer.push_back( new_hole );
}
}
// build hole list for pads (assumed always through holes)
if( !aExcludeThroughHoles || aGenerateNPTH_list )
{
for( MODULE* module = m_pcb->m_Modules; module; module = module->Next() )
{
// Read and analyse pads
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
if( ! aGenerateNPTH_list &&
pad->GetAttribute() == PAD_HOLE_NOT_PLATED &&
! aMerge_PTH_NPTH )
continue;
if( aGenerateNPTH_list && pad->GetAttribute() != PAD_HOLE_NOT_PLATED )
continue;
if( pad->GetDrillSize().x == 0 )
continue;
new_hole.m_Hole_NotPlated = (pad->GetAttribute() == PAD_HOLE_NOT_PLATED);
new_hole.m_Tool_Reference = -1; // Flag is: Not initialized
new_hole.m_Hole_Orient = pad->GetOrientation();
new_hole.m_Hole_Shape = 0; // hole shape: round
new_hole.m_Hole_Diameter = std::min( pad->GetDrillSize().x, pad->GetDrillSize().y );
new_hole.m_Hole_Size.x = new_hole.m_Hole_Size.y = new_hole.m_Hole_Diameter;
if( pad->GetDrillShape() != PAD_DRILL_CIRCLE )
new_hole.m_Hole_Shape = 1; // oval flag set
new_hole.m_Hole_Size = pad->GetDrillSize();
new_hole.m_Hole_Pos = pad->GetPosition(); // hole position
new_hole.m_Hole_Bottom_Layer = B_Cu;
new_hole.m_Hole_Top_Layer = F_Cu;// pad holes are through holes
m_holeListBuffer.push_back( new_hole );
}
}
}
// Sort holes per increasing diameter value
sort( m_holeListBuffer.begin(), m_holeListBuffer.end(), CmpHoleDiameterValue );
// build the tool list
int LastHole = -1; /* Set to not initialized (this is a value not used
* for m_holeListBuffer[ii].m_Hole_Diameter) */
DRILL_TOOL new_tool( 0 );
unsigned jj;
for( unsigned ii = 0; ii < m_holeListBuffer.size(); ii++ )
{
if( m_holeListBuffer[ii].m_Hole_Diameter != LastHole )
{
new_tool.m_Diameter = ( m_holeListBuffer[ii].m_Hole_Diameter );
m_toolListBuffer.push_back( new_tool );
LastHole = new_tool.m_Diameter;
}
jj = m_toolListBuffer.size();
if( jj == 0 )
continue; // Should not occurs
m_holeListBuffer[ii].m_Tool_Reference = jj; // Tool value Initialized (value >= 1)
m_toolListBuffer.back().m_TotalCount++;
if( m_holeListBuffer[ii].m_Hole_Shape )
m_toolListBuffer.back().m_OvalCount++;
}
}
bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
{
TRACK* track;
wxPoint delta; // length on X and Y axis of segments
LSET layerMask;
int net_code_ref;
wxPoint shape_pos;
NETCLASSPTR netclass = aRefSeg->GetNetClass();
BOARD_DESIGN_SETTINGS& dsnSettings = m_pcb->GetDesignSettings();
/* In order to make some calculations more easier or faster,
* pads and tracks coordinates will be made relative to the reference segment origin
*/
wxPoint origin = aRefSeg->GetStart(); // origin will be the origin of other coordinates
m_segmEnd = delta = aRefSeg->GetEnd() - origin;
m_segmAngle = 0;
layerMask = aRefSeg->GetLayerSet();
net_code_ref = aRefSeg->GetNetCode();
// Phase 0 : Test vias
if( aRefSeg->Type() == PCB_VIA_T )
{
const VIA *refvia = static_cast<const VIA*>( aRefSeg );
// test if the via size is smaller than minimum
if( refvia->GetViaType() == VIA_MICROVIA )
{
if( refvia->GetWidth() < dsnSettings.m_MicroViasMinSize )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_MICROVIA, m_currentMarker );
return false;
}
if( refvia->GetDrillValue() < dsnSettings.m_MicroViasMinDrill )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_MICROVIA_DRILL, m_currentMarker );
return false;
}
}
else
{
if( refvia->GetWidth() < dsnSettings.m_ViasMinSize )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_VIA, m_currentMarker );
return false;
}
if( refvia->GetDrillValue() < dsnSettings.m_ViasMinDrill )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_VIA_DRILL, m_currentMarker );
return false;
}
}
// test if via's hole is bigger than its diameter
// This test is necessary since the via hole size and width can be modified
// and a default via hole can be bigger than some vias sizes
if( refvia->GetDrillValue() > refvia->GetWidth() )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_VIA_HOLE_BIGGER, m_currentMarker );
return false;
}
// For microvias: test if they are blind vias and only between 2 layers
// because they are used for very small drill size and are drill by laser
// and **only one layer** can be drilled
if( refvia->GetViaType() == VIA_MICROVIA )
{
LAYER_ID layer1, layer2;
bool err = true;
refvia->LayerPair( &layer1, &layer2 );
if( layer1 > layer2 )
std::swap( layer1, layer2 );
if( layer2 == B_Cu && layer1 == m_pcb->GetDesignSettings().GetCopperLayerCount() - 2 )
err = false;
else if( layer1 == F_Cu && layer2 == In1_Cu )
err = false;
if( err )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR, m_currentMarker );
return false;
}
}
}
else // This is a track segment
{
if( aRefSeg->GetWidth() < dsnSettings.m_TrackMinWidth )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_TRACK_WIDTH, m_currentMarker );
return false;
}
}
// for a non horizontal or vertical segment Compute the segment angle
// in tenths of degrees and its length
if( delta.x || delta.y )
{
// Compute the segment angle in 0,1 degrees
m_segmAngle = ArcTangente( delta.y, delta.x );
// Compute the segment length: we build an equivalent rotated segment,
// this segment is horizontal, therefore dx = length
RotatePoint( &delta, m_segmAngle ); // delta.x = length, delta.y = 0
}
m_segmLength = delta.x;
/******************************************/
/* Phase 1 : test DRC track to pads : */
/******************************************/
/* Use a dummy pad to test DRC tracks versus holes, for pads not on all copper layers
* but having a hole
* This dummy pad has the size and shape of the hole
* to test tracks to pad hole DRC, using checkClearanceSegmToPad test function.
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( m_pcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
dummypad.SetLayerSet( LSET::AllCuMask() ); // Ensure the hole is on all layers
// Compute the min distance to pads
if( testPads )
{
unsigned pad_count = m_pcb->GetPadCount();
for( unsigned ii = 0; ii<pad_count; ++ii )
{
D_PAD* pad = m_pcb->GetPad( ii );
/* No problem if pads are on an other layer,
* But if a drill hole exists (a pad on a single layer can have a hole!)
* we must test the hole
*/
if( !( pad->GetLayerSet() & layerMask ).any() )
{
/* We must test the pad hole. In order to use the function
* checkClearanceSegmToPad(),a pseudo pad is used, with a shape and a
* size like the hole
*/
if( pad->GetDrillSize().x == 0 )
continue;
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetPosition( pad->GetPosition() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetOrientation( pad->GetOrientation() );
m_padToTestPos = dummypad.GetPosition() - origin;
if( !checkClearanceSegmToPad( &dummypad, aRefSeg->GetWidth(),
netclass->GetClearance() ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_THROUGH_HOLE, m_currentMarker );
return false;
}
continue;
}
// The pad must be in a net (i.e pt_pad->GetNet() != 0 )
// but no problem if the pad netcode is the current netcode (same net)
if( pad->GetNetCode() // the pad must be connected
&& net_code_ref == pad->GetNetCode() ) // the pad net is the same as current net -> Ok
continue;
// DRC for the pad
shape_pos = pad->ShapePos();
m_padToTestPos = shape_pos - origin;
if( !checkClearanceSegmToPad( pad, aRefSeg->GetWidth(), aRefSeg->GetClearance( pad ) ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_PAD, m_currentMarker );
return false;
}
}
}
/***********************************************/
/* Phase 2: test DRC with other track segments */
/***********************************************/
// At this point the reference segment is the X axis
// Test the reference segment with other track segments
wxPoint segStartPoint;
wxPoint segEndPoint;
for( track = aStart; track; track = track->Next() )
{
// No problem if segments have the same net code:
if( net_code_ref == track->GetNetCode() )
continue;
// No problem if segment are on different layers :
if( !( layerMask & track->GetLayerSet() ).any() )
continue;
// the minimum distance = clearance plus half the reference track
// width plus half the other track's width
int w_dist = aRefSeg->GetClearance( track );
w_dist += (aRefSeg->GetWidth() + track->GetWidth()) / 2;
// Due to many double to int conversions during calculations, which
// create rounding issues,
// the exact clearance margin cannot be really known.
// To avoid false bad DRC detection due to these rounding issues,
// slightly decrease the w_dist (remove one nanometer is enough !)
w_dist -= 1;
// If the reference segment is a via, we test it here
if( aRefSeg->Type() == PCB_VIA_T )
{
delta = track->GetEnd() - track->GetStart();
segStartPoint = aRefSeg->GetStart() - track->GetStart();
if( track->Type() == PCB_VIA_T )
{
// Test distance between two vias, i.e. two circles, trivial case
if( EuclideanNorm( segStartPoint ) < w_dist )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_VIA_NEAR_VIA, m_currentMarker );
return false;
}
}
else // test via to segment
{
// Compute l'angle du segment a tester;
double angle = ArcTangente( delta.y, delta.x );
// Compute new coordinates ( the segment become horizontal)
RotatePoint( &delta, angle );
RotatePoint( &segStartPoint, angle );
if( !checkMarginToCircle( segStartPoint, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( track, aRefSeg,
DRCE_VIA_NEAR_TRACK, m_currentMarker );
return false;
}
}
continue;
}
/* We compute segStartPoint, segEndPoint = starting and ending point coordinates for
* the segment to test in the new axis : the new X axis is the
* reference segment. We must translate and rotate the segment to test
*/
segStartPoint = track->GetStart() - origin;
segEndPoint = track->GetEnd() - origin;
RotatePoint( &segStartPoint, m_segmAngle );
RotatePoint( &segEndPoint, m_segmAngle );
if( track->Type() == PCB_VIA_T )
{
if( checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
continue;
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_NEAR_VIA, m_currentMarker );
return false;
}
/* We have changed axis:
* the reference segment is Horizontal.
* 3 cases : the segment to test can be parallel, perpendicular or have an other direction
*/
if( segStartPoint.y == segEndPoint.y ) // parallel segments
{
if( abs( segStartPoint.y ) >= w_dist )
continue;
// Ensure segStartPoint.x <= segEndPoint.x
if( segStartPoint.x > segEndPoint.x )
std::swap( segStartPoint.x, segEndPoint.x );
if( segStartPoint.x > (-w_dist) && segStartPoint.x < (m_segmLength + w_dist) ) /* possible error drc */
{
// the start point is inside the reference range
// X........
// O--REF--+
// Fine test : we consider the rounded shape of each end of the track segment:
if( segStartPoint.x >= 0 && segStartPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS2, m_currentMarker );
return false;
}
}
if( segEndPoint.x > (-w_dist) && segEndPoint.x < (m_segmLength + w_dist) )
{
// the end point is inside the reference range
// .....X
// O--REF--+
// Fine test : we consider the rounded shape of the ends
if( segEndPoint.x >= 0 && segEndPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS3, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS4, m_currentMarker );
return false;
}
}
if( segStartPoint.x <=0 && segEndPoint.x >= 0 )
{
// the segment straddles the reference range (this actually only
// checks if it straddles the origin, because the other cases where already
// handled)
// X.............X
// O--REF--+
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_SEGMENTS_TOO_CLOSE, m_currentMarker );
return false;
}
}
else if( segStartPoint.x == segEndPoint.x ) // perpendicular segments
{
if( ( segStartPoint.x <= (-w_dist) ) || ( segStartPoint.x >= (m_segmLength + w_dist) ) )
continue;
// Test if segments are crossing
if( segStartPoint.y > segEndPoint.y )
std::swap( segStartPoint.y, segEndPoint.y );
if( (segStartPoint.y < 0) && (segEndPoint.y > 0) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACKS_CROSSING, m_currentMarker );
return false;
}
// At this point the drc error is due to an end near a reference segm end
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM2, m_currentMarker );
return false;
}
}
else // segments quelconques entre eux
{
// calcul de la "surface de securite du segment de reference
// First rought 'and fast) test : the track segment is like a rectangle
m_xcliplo = m_ycliplo = -w_dist;
m_xcliphi = m_segmLength + w_dist;
m_ycliphi = w_dist;
// A fine test is needed because a serment is not exactly a
// rectangle, it has rounded ends
if( !checkLine( segStartPoint, segEndPoint ) )
{
/* 2eme passe : the track has rounded ends.
* we must a fine test for each rounded end and the
* rectangular zone
*/
m_xcliplo = 0;
m_xcliphi = m_segmLength;
if( !checkLine( segStartPoint, segEndPoint ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM3, m_currentMarker );
return false;
}
else // The drc error is due to the starting or the ending point of the reference segment
{
// Test the starting and the ending point
segStartPoint = track->GetStart();
segEndPoint = track->GetEnd();
delta = segEndPoint - segStartPoint;
// Compute the segment orientation (angle) en 0,1 degre
double angle = ArcTangente( delta.y, delta.x );
// Compute the segment length: delta.x = length after rotation
RotatePoint( &delta, angle );
/* Comute the reference segment coordinates relatives to a
* X axis = current tested segment
*/
wxPoint relStartPos = aRefSeg->GetStart() - segStartPoint;
wxPoint relEndPos = aRefSeg->GetEnd() - segStartPoint;
RotatePoint( &relStartPos, angle );
RotatePoint( &relEndPos, angle );
if( !checkMarginToCircle( relStartPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM4, m_currentMarker );
return false;
}
if( !checkMarginToCircle( relEndPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM5, m_currentMarker );
return false;
}
}
}
}
}
return true;
}
bool DRC::doPadToPadsDrc( D_PAD* aRefPad, D_PAD** aStart, D_PAD** aEnd, int x_limit )
{
const static LSET all_cu = LSET::AllCuMask();
LSET layerMask = aRefPad->GetLayerSet() & all_cu;
/* used to test DRC pad to holes: this dummy pad has the size and shape of the hole
* to test pad to pad hole DRC, using the pad to pad DRC test function.
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( m_pcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
// Ensure the hole is on all copper layers
dummypad.SetLayerSet( all_cu | dummypad.GetLayerSet() );
// Use the minimal local clearance value for the dummy pad.
// The clearance of the active pad will be used as minimum distance to a hole
// (a value = 0 means use netclass value)
dummypad.SetLocalClearance( 1 );
for( D_PAD** pad_list = aStart; pad_list<aEnd; ++pad_list )
{
D_PAD* pad = *pad_list;
if( pad == aRefPad )
continue;
// We can stop the test when pad->GetPosition().x > x_limit
// because the list is sorted by X values
if( pad->GetPosition().x > x_limit )
break;
// No problem if pads which are on copper layers are on different copper layers,
// (pads can be only on a technical layer, to build complex pads)
// but their hole (if any ) can create DRC error because they are on all
// copper layers, so we test them
if( ( pad->GetLayerSet() & layerMask ) == 0 &&
( pad->GetLayerSet() & all_cu ) != 0 &&
( aRefPad->GetLayerSet() & all_cu ) != 0 )
{
// if holes are in the same location and have the same size and shape,
// this can be accepted
if( pad->GetPosition() == aRefPad->GetPosition()
&& pad->GetDrillSize() == aRefPad->GetDrillSize()
&& pad->GetDrillShape() == aRefPad->GetDrillShape() )
{
if( aRefPad->GetDrillShape() == PAD_DRILL_SHAPE_CIRCLE )
continue;
// for oval holes: must also have the same orientation
if( pad->GetOrientation() == aRefPad->GetOrientation() )
continue;
}
/* Here, we must test clearance between holes and pads
* dummy pad size and shape is adjusted to pad drill size and shape
*/
if( pad->GetDrillSize().x )
{
// pad under testing has a hole, test this hole against pad reference
dummypad.SetPosition( pad->GetPosition() );
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetOrientation( pad->GetOrientation() );
if( !checkClearancePadToPad( aRefPad, &dummypad ) )
{
// here we have a drc error on pad!
m_currentMarker = fillMarker( pad, aRefPad,
DRCE_HOLE_NEAR_PAD, m_currentMarker );
return false;
}
}
if( aRefPad->GetDrillSize().x ) // pad reference has a hole
{
dummypad.SetPosition( aRefPad->GetPosition() );
dummypad.SetSize( aRefPad->GetDrillSize() );
dummypad.SetShape( aRefPad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetOrientation( aRefPad->GetOrientation() );
if( !checkClearancePadToPad( pad, &dummypad ) )
{
// here we have a drc error on aRefPad!
m_currentMarker = fillMarker( aRefPad, pad,
DRCE_HOLE_NEAR_PAD, m_currentMarker );
return false;
}
}
continue;
}
// The pad must be in a net (i.e pt_pad->GetNet() != 0 ),
// But no problem if pads have the same netcode (same net)
if( pad->GetNetCode() && ( aRefPad->GetNetCode() == pad->GetNetCode() ) )
continue;
// if pads are from the same footprint
if( pad->GetParent() == aRefPad->GetParent() )
{
// and have the same pad number ( equivalent pads )
// one can argue that this 2nd test is not necessary, that any
// two pads from a single module are acceptable. This 2nd test
// should eventually be a configuration option.
if( pad->PadNameEqual( aRefPad ) )
continue;
}
// if either pad has no drill and is only on technical layers, not a clearance violation
if( ( ( pad->GetLayerSet() & layerMask ) == 0 && !pad->GetDrillSize().x ) ||
( ( aRefPad->GetLayerSet() & layerMask ) == 0 && !aRefPad->GetDrillSize().x ) )
{
continue;
}
if( !checkClearancePadToPad( aRefPad, pad ) )
{
// here we have a drc error!
m_currentMarker = fillMarker( aRefPad, pad, DRCE_PAD_NEAR_PAD1, m_currentMarker );
return false;
}
}
return true;
}
void PlotLayerOutlines( BOARD *aBoard, PLOTTER* aPlotter,
LAYER_MSK aLayerMask, const PCB_PLOT_PARAMS& aPlotOpt )
{
BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
itemplotter.SetLayerMask( aLayerMask );
CPOLYGONS_LIST outlines;
for( LAYER_NUM layer = FIRST_LAYER; layer < NB_PCB_LAYERS; layer++ )
{
LAYER_MSK layer_mask = GetLayerMask( layer );
if( (aLayerMask & layer_mask ) == 0 )
continue;
outlines.RemoveAllContours();
aBoard->ConvertBrdLayerToPolygonalContours( layer, outlines );
// Merge all overlapping polygons.
KI_POLYGON_SET kpolygons;
KI_POLYGON_SET ktmp;
outlines.ExportTo( ktmp );
kpolygons += ktmp;
// Plot outlines
std::vector< wxPoint > cornerList;
for( unsigned ii = 0; ii < kpolygons.size(); ii++ )
{
KI_POLYGON polygon = kpolygons[ii];
// polygon contains only one polygon, but it can have holes linked by
// overlapping segments.
// To plot clean outlines, we have to break this polygon into more polygons with
// no overlapping segments, using Clipper, because boost::polygon
// does not allow that
ClipperLib::Path raw_polygon;
ClipperLib::Paths normalized_polygons;
for( unsigned ic = 0; ic < polygon.size(); ic++ )
{
KI_POLY_POINT corner = *(polygon.begin() + ic);
raw_polygon.push_back( ClipperLib::IntPoint( corner.x(), corner.y() ) );
}
ClipperLib::SimplifyPolygon( raw_polygon, normalized_polygons );
// Now we have one or more basic polygons: plot each polygon
for( unsigned ii = 0; ii < normalized_polygons.size(); ii++ )
{
ClipperLib::Path& polygon = normalized_polygons[ii];
cornerList.clear();
for( unsigned jj = 0; jj < polygon.size(); jj++ )
cornerList.push_back( wxPoint( polygon[jj].X , polygon[jj].Y ) );
// Ensure the polygon is closed
if( cornerList[0] != cornerList[cornerList.size()-1] )
cornerList.push_back( cornerList[0] );
aPlotter->PlotPoly( cornerList, NO_FILL );
}
}
// Plot pad holes
if( aPlotOpt.GetDrillMarksType() != PCB_PLOT_PARAMS::NO_DRILL_SHAPE )
{
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
wxSize hole = pad->GetDrillSize();
if( hole.x == 0 || hole.y == 0 )
continue;
if( hole.x == hole.y )
aPlotter->Circle( pad->GetPosition(), hole.x, NO_FILL );
else
{
wxPoint drl_start, drl_end;
int width;
pad->GetOblongDrillGeometry( drl_start, drl_end, width );
aPlotter->ThickSegment( pad->GetPosition() + drl_start,
pad->GetPosition() + drl_end, width, SKETCH );
}
}
}
}
// Plot vias holes
for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
{
const VIA* via = dyn_cast<const VIA*>( track );
if( via && via->IsOnLayer( layer ) ) // via holes can be not through holes
{
aPlotter->Circle( via->GetPosition(), via->GetDrillValue(), NO_FILL );
}
}
}
}
