RetType dispatchByItemKind_gen(Inst item,Visitor& vis) { switch(item.kind()) { case BRIG_KIND_INST_ADDR: return vis(InstAddr(item)); case BRIG_KIND_INST_ATOMIC: return vis(InstAtomic(item)); case BRIG_KIND_INST_BASIC: return vis(InstBasic(item)); case BRIG_KIND_INST_BR: return vis(InstBr(item)); case BRIG_KIND_INST_CMP: return vis(InstCmp(item)); case BRIG_KIND_INST_CVT: return vis(InstCvt(item)); case BRIG_KIND_INST_IMAGE: return vis(InstImage(item)); case BRIG_KIND_INST_LANE: return vis(InstLane(item)); case BRIG_KIND_INST_MEM: return vis(InstMem(item)); case BRIG_KIND_INST_MEM_FENCE: return vis(InstMemFence(item)); case BRIG_KIND_INST_MOD: return vis(InstMod(item)); case BRIG_KIND_INST_QUERY_IMAGE: return vis(InstQueryImage(item)); case BRIG_KIND_INST_QUERY_SAMPLER: return vis(InstQuerySampler(item)); case BRIG_KIND_INST_QUEUE: return vis(InstQueue(item)); case BRIG_KIND_INST_SEG: return vis(InstSeg(item)); case BRIG_KIND_INST_SEG_CVT: return vis(InstSegCvt(item)); case BRIG_KIND_INST_SIGNAL: return vis(InstSignal(item)); case BRIG_KIND_INST_SOURCE_TYPE: return vis(InstSourceType(item)); default: assert(false); break; } return RetType(); }
int main(int argc, char **argv) { Manager manager; PropList props; PROCESSOR_PATH(props) = "../../data/procs/op1.xml"; CACHE_CONFIG_PATH(props) = "../../data/caches/inst-64x16x1.xml"; try { // Load program if(argc < 2) { cerr << "ERROR: no argument.\n" << "Syntax is : test_ipet <executable>\n"; return 2; } WorkSpace *fw = manager.load(argv[1], props); assert(fw); // Display information cout << "PLATFORM INFORMATION\n"; Platform *pf = fw->platform(); cout << "Platform : " << pf->identification().name() << '\n'; cout << '\n'; // Display registers cout << "REGISTERS\n"; for(int i = 0; i < pf->banks().count(); i++) { const hard::RegBank *bank = pf->banks()[i]; cout << "Bank " << bank->name() << ", " << bank->size() << "bits, " << bank->count() << " registers, " << reg_kinds[bank->kind()]; for(int j = 0; j < bank->registers().count(); j++) { if(j % 8 == 0) cout << "\n\t"; else cout << ", "; cout << bank->registers()[j]->name(); } cout << '\n'; } cout << '\n'; // Display cache cout << "CACHE CONFIGURATION\n"; const CacheConfiguration& cconf(pf->cache()); display_cache_level(1, cconf.instCache(), cconf.dataCache()); cout << '\n'; // Display some instructions fw->require(DECODED_TEXT); cout << "READ/WRITTEN REGS TEST\n"; String label("main"); Inst *inst = fw->process()->findInstAt("main"); //fw->findLabel(label)); if(!inst) throw new otawa::Exception(CString("no main in this file ?")); for(int i = 0; i < 10; i++, inst = inst->nextInst()) { cout << '\n' << inst->address() << ": " << inst << " (" << io::hex(inst->kind()) << ")\n"; const elm::genstruct::Table<hard::Register *>& reads = inst->readRegs(); cout << "\tread registers : "; for(int i = 0; i < reads.count(); i++) cout << reads[i] << ' '; cout << '\n'; const elm::genstruct::Table<hard::Register *>& writes = inst->writtenRegs(); cout << "\twritten registers : "; for(int i = 0; i < writes.count(); i++) cout << writes[i] << ' '; cout << '\n'; } cout << io::endl; // Processor load test cout << "Processor load test\n"; //pf->loadProcessor("proc.xml"); const hard::Processor *proc = pf->processor(); if(!proc) cout << "NO PROCESSOR !\n"; else { cout << "arch = " << proc->getArch() << io::endl; cout << "model = " << proc->getModel() << io::endl; cout << "builder = " << proc->getBuilder() << io::endl; cout <<"stages =\n"; const elm::genstruct::Table<hard::Stage *>& stages = proc->getStages(); for(int i = 0; i< stages.count(); i++) { cout << '\t' << stages[i]->getName() << " " << stages[i]->getType() << " " << stages[i]->getWidth() << " " << stages[i]->getLatency() << " " << io::pointer(stages[i]) << io::endl; const elm::genstruct::Table<hard::FunctionalUnit *>& fus = stages[i]->getFUs(); if(fus) { cout << "\tfus=\n"; for(int i = 0; i < fus.count(); i++) cout << "\t\t" << fus[i]->getName() << ' ' << fus[i]->getWidth() << ' ' << fus[i]->getLatency() << ' ' << fus[i]->isPipelined() << io::endl; } const elm::genstruct::Table<hard::Dispatch *>& dispatch = stages[i]->getDispatch(); if(dispatch) { cout << "\tdispatch=\n"; for(int i = 0; i < dispatch.count(); i++) cout << "\t\t" << dispatch[i]->getType() << ' ' << dispatch[i]->getFU()->getName() << io::endl; } } cout << "queues =\n"; const elm::genstruct::Table<hard::Queue *>& queues = proc->getQueues(); for(int i = 0; i< queues.count(); i++) { cout << '\t' << queues[i]->getName() << " " << queues[i]->getSize() << " " << queues[i]->getInput()->getName() << " (" << io::pointer(queues[i]->getInput()) << ") " << queues[i]->getOutput()->getName() << " (" << io::pointer(queues[i]->getOutput()) << ")" << io::endl; const elm::genstruct::Table<hard::Stage *>& intern = queues[i]->getIntern(); if(intern) { cout << "\tintern=\n"; for(int i = 0; i < intern.count(); i++) cout << "\t\t" << intern[i]->getName() << " (" << io::pointer(intern[i]) << ')' << io::endl; } } } } catch(elm::Exception& e) { cerr << "ERROR: " << e.message() << '\n'; return 1; } return 0; }
bool ValidatorImpl::ValidateBrigInstFields(Inst item) const { unsigned kind = item.kind(); switch (kind) { case BRIG_KIND_INST_ADDR: { InstAddr it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstAddr", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstAddr", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstAddr", "operands"); validate_BrigSegment(item, it.brig()->segment, "InstAddr", "segment"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstAddr", "reserved"); } } break; case BRIG_KIND_INST_ATOMIC: { InstAtomic it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstAtomic", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstAtomic", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstAtomic", "operands"); validate_BrigSegment(item, it.brig()->segment, "InstAtomic", "segment"); validate_BrigMemoryOrder(item, it.brig()->memoryOrder, "InstAtomic", "memoryOrder"); validate_BrigMemoryScope(item, it.brig()->memoryScope, "InstAtomic", "memoryScope"); validate_BrigAtomicOperation(item, it.brig()->atomicOperation, "InstAtomic", "atomicOperation"); validate_fld_EquivClass(item, it.brig()->equivClass, "InstAtomic", "equivClass"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstAtomic", "reserved"); } } break; case BRIG_KIND_INST_BASIC: { InstBasic it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstBasic", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstBasic", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstBasic", "operands"); } break; case BRIG_KIND_INST_BR: { InstBr it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstBr", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstBr", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstBr", "operands"); validate_BrigWidth(item, it.brig()->width, "InstBr", "width"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstBr", "reserved"); } } break; case BRIG_KIND_INST_CMP: { InstCmp it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstCmp", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstCmp", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstCmp", "operands"); validate_BrigType(item, it.brig()->sourceType, "InstCmp", "sourceType"); validate_BrigAluModifier(item, it.brig()->modifier, "InstCmp", "modifier"); validate_BrigCompareOperation(item, it.brig()->compare, "InstCmp", "compare"); validate_BrigPack(item, it.brig()->pack, "InstCmp", "pack"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstCmp", "reserved"); } } break; case BRIG_KIND_INST_CVT: { InstCvt it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstCvt", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstCvt", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstCvt", "operands"); validate_BrigType(item, it.brig()->sourceType, "InstCvt", "sourceType"); validate_BrigAluModifier(item, it.brig()->modifier, "InstCvt", "modifier"); validate_BrigRound(item, it.brig()->round, "InstCvt", "round"); } break; case BRIG_KIND_INST_IMAGE: { InstImage it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstImage", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstImage", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstImage", "operands"); validate_BrigType(item, it.brig()->imageType, "InstImage", "imageType"); validate_BrigType(item, it.brig()->coordType, "InstImage", "coordType"); validate_BrigImageGeometry(item, it.brig()->geometry, "InstImage", "geometry"); validate_fld_EquivClass(item, it.brig()->equivClass, "InstImage", "equivClass"); validate_fld_Reserved(item, it.brig()->reserved, "InstImage", "reserved"); } break; case BRIG_KIND_INST_LANE: { InstLane it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstLane", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstLane", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstLane", "operands"); validate_BrigType(item, it.brig()->sourceType, "InstLane", "sourceType"); validate_BrigWidth(item, it.brig()->width, "InstLane", "width"); validate_fld_Reserved(item, it.brig()->reserved, "InstLane", "reserved"); } break; case BRIG_KIND_INST_MEM: { InstMem it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstMem", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstMem", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstMem", "operands"); validate_BrigSegment(item, it.brig()->segment, "InstMem", "segment"); validate_BrigAlignment(item, it.brig()->align, "InstMem", "align"); validate_fld_EquivClass(item, it.brig()->equivClass, "InstMem", "equivClass"); validate_BrigWidth(item, it.brig()->width, "InstMem", "width"); validate_BrigMemoryModifier(item, it.brig()->modifier, "InstMem", "modifier"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstMem", "reserved"); } } break; case BRIG_KIND_INST_MEM_FENCE: { InstMemFence it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstMemFence", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstMemFence", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstMemFence", "operands"); validate_BrigMemoryOrder(item, it.brig()->memoryOrder, "InstMemFence", "memoryOrder"); validate_BrigMemoryScope(item, it.brig()->globalSegmentMemoryScope, "InstMemFence", "globalSegmentMemoryScope"); validate_BrigMemoryScope(item, it.brig()->groupSegmentMemoryScope, "InstMemFence", "groupSegmentMemoryScope"); validate_BrigMemoryScope(item, it.brig()->imageSegmentMemoryScope, "InstMemFence", "imageSegmentMemoryScope"); } break; case BRIG_KIND_INST_MOD: { InstMod it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstMod", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstMod", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstMod", "operands"); validate_BrigAluModifier(item, it.brig()->modifier, "InstMod", "modifier"); validate_BrigRound(item, it.brig()->round, "InstMod", "round"); validate_BrigPack(item, it.brig()->pack, "InstMod", "pack"); validate_fld_Reserved(item, it.brig()->reserved, "InstMod", "reserved"); } break; case BRIG_KIND_INST_QUERY_IMAGE: { InstQueryImage it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstQueryImage", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstQueryImage", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstQueryImage", "operands"); validate_BrigType(item, it.brig()->imageType, "InstQueryImage", "imageType"); validate_BrigImageGeometry(item, it.brig()->geometry, "InstQueryImage", "geometry"); validate_BrigImageQuery(item, it.brig()->imageQuery, "InstQueryImage", "imageQuery"); } break; case BRIG_KIND_INST_QUERY_SAMPLER: { InstQuerySampler it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstQuerySampler", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstQuerySampler", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstQuerySampler", "operands"); validate_BrigSamplerQuery(item, it.brig()->samplerQuery, "InstQuerySampler", "samplerQuery"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstQuerySampler", "reserved"); } } break; case BRIG_KIND_INST_QUEUE: { InstQueue it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstQueue", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstQueue", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstQueue", "operands"); validate_BrigSegment(item, it.brig()->segment, "InstQueue", "segment"); validate_BrigMemoryOrder(item, it.brig()->memoryOrder, "InstQueue", "memoryOrder"); validate_fld_Reserved(item, it.brig()->reserved, "InstQueue", "reserved"); } break; case BRIG_KIND_INST_SEG: { InstSeg it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstSeg", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstSeg", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstSeg", "operands"); validate_BrigSegment(item, it.brig()->segment, "InstSeg", "segment"); for (unsigned i = 0; i < 3; i++) { validate_fld_Reserved(item, it.brig()->reserved[i], "InstSeg", "reserved"); } } break; case BRIG_KIND_INST_SEG_CVT: { InstSegCvt it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstSegCvt", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstSegCvt", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstSegCvt", "operands"); validate_BrigType(item, it.brig()->sourceType, "InstSegCvt", "sourceType"); validate_BrigSegment(item, it.brig()->segment, "InstSegCvt", "segment"); validate_BrigSegCvtModifier(item, it.brig()->modifier, "InstSegCvt", "modifier"); } break; case BRIG_KIND_INST_SIGNAL: { InstSignal it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstSignal", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstSignal", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstSignal", "operands"); validate_BrigType(item, it.brig()->signalType, "InstSignal", "signalType"); validate_BrigMemoryOrder(item, it.brig()->memoryOrder, "InstSignal", "memoryOrder"); validate_BrigAtomicOperation(item, it.brig()->signalOperation, "InstSignal", "signalOperation"); } break; case BRIG_KIND_INST_SOURCE_TYPE: { InstSourceType it = item; validate_BrigOpcode(item, it.brig()->base.opcode, "InstSourceType", "opcode"); validate_BrigType(item, it.brig()->base.type, "InstSourceType", "type"); validate_BrigDataOffsetOperandList(item, it.brig()->base.operands, "InstSourceType", "operands"); validate_BrigType(item, it.brig()->sourceType, "InstSourceType", "sourceType"); validate_fld_Reserved(item, it.brig()->reserved, "InstSourceType", "reserved"); } break; default: return false; // not found } // switch return true; // found and validated }
void setBrigProp(Inst inst, unsigned propId, unsigned val, bool ignoreErrors) { using namespace HSAIL_PROPS; switch(inst.kind()) { case BRIG_KIND_INST_ADDR: { InstAddr it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SEGMENT: it.segment() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_ATOMIC: { InstAtomic it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SEGMENT: it.segment() = val; break; case PROP_MEMORYORDER: it.memoryOrder() = val; break; case PROP_MEMORYSCOPE: it.memoryScope() = val; break; case PROP_ATOMICOPERATION: it.atomicOperation() = val; break; case PROP_EQUIVCLASS: it.equivClass() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_BASIC: { InstBasic it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_BR: { InstBr it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_WIDTH: it.width() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_CMP: { InstCmp it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SOURCETYPE: it.sourceType() = val; break; case PROP_FTZ: it.modifier().ftz() = (val != 0); break; case PROP_COMPARE: it.compare() = val; break; case PROP_PACK: it.pack() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_CVT: { InstCvt it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SOURCETYPE: it.sourceType() = val; break; case PROP_FTZ: it.modifier().ftz() = (val != 0); break; case PROP_ROUND: it.round() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_IMAGE: { InstImage it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_IMAGETYPE: it.imageType() = val; break; case PROP_COORDTYPE: it.coordType() = val; break; case PROP_GEOMETRY: it.geometry() = val; break; case PROP_EQUIVCLASS: it.equivClass() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_LANE: { InstLane it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SOURCETYPE: it.sourceType() = val; break; case PROP_WIDTH: it.width() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_MEM: { InstMem it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SEGMENT: it.segment() = val; break; case PROP_ALIGN: it.align() = val; break; case PROP_EQUIVCLASS: it.equivClass() = val; break; case PROP_WIDTH: it.width() = val; break; case PROP_ISCONST: it.modifier().isConst() = (val != 0); break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_MEM_FENCE: { InstMemFence it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_MEMORYORDER: it.memoryOrder() = val; break; case PROP_GLOBALSEGMENTMEMORYSCOPE: it.globalSegmentMemoryScope() = val; break; case PROP_GROUPSEGMENTMEMORYSCOPE: it.groupSegmentMemoryScope() = val; break; case PROP_IMAGESEGMENTMEMORYSCOPE: it.imageSegmentMemoryScope() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_MOD: { InstMod it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_FTZ: it.modifier().ftz() = (val != 0); break; case PROP_ROUND: it.round() = val; break; case PROP_PACK: it.pack() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_QUERY_IMAGE: { InstQueryImage it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_IMAGETYPE: it.imageType() = val; break; case PROP_GEOMETRY: it.geometry() = val; break; case PROP_IMAGEQUERY: it.imageQuery() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_QUERY_SAMPLER: { InstQuerySampler it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SAMPLERQUERY: it.samplerQuery() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_QUEUE: { InstQueue it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SEGMENT: it.segment() = val; break; case PROP_MEMORYORDER: it.memoryOrder() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_SEG: { InstSeg it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SEGMENT: it.segment() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_SEG_CVT: { InstSegCvt it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SOURCETYPE: it.sourceType() = val; break; case PROP_SEGMENT: it.segment() = val; break; case PROP_ISNONULL: it.modifier().isNoNull() = (val != 0); break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_SIGNAL: { InstSignal it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SIGNALTYPE: it.signalType() = val; break; case PROP_MEMORYORDER: it.memoryOrder() = val; break; case PROP_SIGNALOPERATION: it.signalOperation() = val; break; default: assert(ignoreErrors); break; } } break; case BRIG_KIND_INST_SOURCE_TYPE: { InstSourceType it = inst; switch(propId) { case PROP_OPCODE: it.opcode() = val; break; case PROP_TYPE: it.type() = val; break; case PROP_SOURCETYPE: it.sourceType() = val; break; default: assert(ignoreErrors); break; } } break; default: assert(false); // Invalid format break; } }