int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
const MCInstrInfo &MCII,
const MCInst &Inst) const {
unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
if (!SCDesc->isValid())
return 0;
unsigned CPUID = getProcessorID();
while (SCDesc->isVariant()) {
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
SCDesc = getSchedClassDesc(SchedClass);
}
if (SchedClass)
return MCSchedModel::computeInstrLatency(STI, *SCDesc);
llvm_unreachable("unsupported variant scheduling class");
}
Optional<double>
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCInstrInfo &MCII,
const MCInst &Inst) const {
Optional<double> Throughput;
unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
if (!SCDesc->isValid())
return Throughput;
unsigned CPUID = getProcessorID();
while (SCDesc->isVariant()) {
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
SCDesc = getSchedClassDesc(SchedClass);
}
if (SchedClass)
return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
llvm_unreachable("unsupported variant scheduling class");
}
void PatmosDisassembler::adjustSignedImm(MCInst &instr) const {
const MCInstrDesc &MID = MII->get(instr.getOpcode());
bool ImmSigned = isPatmosImmediateSigned(MID.TSFlags);
if (hasPatmosImmediate(MID.TSFlags) && ImmSigned) {
unsigned ImmOpNo = getPatmosImmediateOpNo(MID.TSFlags);
unsigned ImmSize = getPatmosImmediateSize(MID.TSFlags);
uint64_t Value = instr.getOperand(ImmOpNo).getImm();
if (Value & (1 << (ImmSize-1))) {
// sign bit is set => sign-extend
Value |= ~0ULL ^ ((1ULL << ImmSize) - 1);
instr.getOperand(ImmOpNo).setImm(Value);
}
}
}
/// Return whether the insn is solo, i.e., cannot be in a packet.
bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
}
/// Return the Hexagon ISA class for the insn.
unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
MCInst const &MCI) {
const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
}
StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
MCInst const &MCI) {
return MCII.getName(MCI.getOpcode());
}
