void BT::visitPHI(const MachineInstr &PI) { int ThisN = PI.getParent()->getNumber(); if (Trace) dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI; const MachineOperand &MD = PI.getOperand(0); assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition"); RegisterRef DefRR(MD); uint16_t DefBW = ME.getRegBitWidth(DefRR); RegisterCell DefC = ME.getCell(DefRR, Map); if (DefC == RegisterCell::self(DefRR.Reg, DefBW)) // XXX slow return; bool Changed = false; for (unsigned i = 1, n = PI.getNumOperands(); i < n; i += 2) { const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB(); int PredN = PB->getNumber(); if (Trace) dbgs() << " edge " << printMBBReference(*PB) << "->" << printMBBReference(*PI.getParent()); if (!EdgeExec.count(CFGEdge(PredN, ThisN))) { if (Trace) dbgs() << " not executable\n"; continue; } RegisterRef RU = PI.getOperand(i); RegisterCell ResC = ME.getCell(RU, Map); if (Trace) dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ResC << "\n"; Changed |= DefC.meet(ResC, DefRR.Reg); } if (Changed) { if (Trace) dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) << " cell: " << DefC << "\n"; ME.putCell(DefRR, DefC, Map); visitUsesOf(DefRR.Reg); } }