UINT8 c64_currah_speech_cartridge_device::c64_cd_r(address_space &space, offs_t offset, UINT8 data, int sphi2, int ba, int roml, int romh, int io1, int io2)
{
if (!romh)
{
data = m_romh[offset & 0x1fff];
}
else if (!io1)
{
/*
bit description
0
1
2
3
4
5
6
7 SBY
*/
data = m_nsp->sby_r() << 7;
}
if (!space.debugger_access() && (offset == 0xa7f0))
{
m_game = !m_game;
m_exrom = !m_exrom;
}
return data;
}
/* Read/Write common */
void psion_state::io_rw(address_space &space, UINT16 offset)
{
if (space.debugger_access())
return;
switch (offset & 0xffc0)
{
case 0xc0:
/* switch off, CPU goes into standby mode */
m_enable_nmi = 0;
m_stby_pwr = 1;
space.machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_HALT, 1);
break;
case 0x100:
m_pulse = 1;
break;
case 0x140:
m_pulse = 0;
break;
case 0x200:
m_kb_counter = 0;
break;
case 0x180:
beep_set_state(m_beep, 1);
break;
case 0x1c0:
beep_set_state(m_beep, 0);
break;
case 0x240:
if (offset == 0x260 && (m_rom_bank_count || m_ram_bank_count))
{
m_ram_bank=0;
m_rom_bank=0;
update_banks(machine());
}
else
m_kb_counter++;
break;
case 0x280:
if (offset == 0x2a0 && m_ram_bank_count)
{
m_ram_bank++;
update_banks(machine());
}
else
m_enable_nmi = 1;
break;
case 0x2c0:
if (offset == 0x2e0 && m_rom_bank_count)
{
m_rom_bank++;
update_banks(machine());
}
else
m_enable_nmi = 0;
break;
}
}
UINT8 a2bus_pcxporter_device::read_c800(address_space &space, UINT16 offset)
{
// printf("Read C800 at %x\n", offset + 0xc800);
if (offset < 0x400)
{
return m_c800_ram[offset];
}
else
{
UINT8 rv;
switch (offset)
{
case 0x700:
return m_offset & 0xff;
case 0x701:
return (m_offset >> 8) & 0xff;
case 0x702:
return (m_offset >> 16) & 0xff;
case 0x703: // read with increment
rv = m_ram[m_offset];
// don't increment if the debugger's reading
if (!space.debugger_access())
{
m_offset++;
}
return rv;
case 0x704: // read w/o increment
rv = m_ram[m_offset];
return rv;
default:
//printf("Read $C800 at %x\n", offset + 0xc800);
break;
}
return m_regs[offset];
}
}
