void on_timed_event()
{
wait(timed_event);
cout << "on_timed_event() awoke\n";
sc_assert( sig1.read() == 1 );
sc_assert( sig2.read() == 2 );
sc_assert( sig3.read() == 3 );
sc_assert( sig4.read() == 0 );
sc_assert( sc_time_stamp() == sc_time(1234, SC_NS) );
}
void on_immed_event()
{
wait(immed_event);
cout << "on_immed_event() awoke\n";
// Should run in 1st eval phase after pause
sc_assert( sig4.read() == 0 );
}
void on_delta_event()
{
wait(delta_event);
cout << "on_delta_event() awoke\n";
// Should run in 2nd eval phase after pause
sc_assert( sig4.read() == 4 );
}
void trans() {
reg1 = reg1.read() ^ 1;
reg2 = reg2.read() + 1;
reg3 = reg3.read() + 1;
reg4 = reg4.read() + 1;
reg5 = reg5.read() + 1;
reg6 = reg6.read() * 2 + 1;
reg9 = reg9.read() + 1;
}
void gen() {
o1 = reg1.read() ^ true;
o2 = reg2.read() + 1;
o3 = reg3.read() + 1;
o4 = reg4.read() + 1;
o5 = reg5.read() + 1;
o6 = reg6.read() + 1;
io1 = reg6.read() * 2 + 1;
io4 = reg9.read() + 1;
}
void print(){
cout << "A : " << ain.read() << endl;
cout << "B : " << bin.read() << endl;
cout << "Operation : " << operation.read() << endl;
cout << "Result : " << sum.read() << endl;
cout << "Overflow : " << (owf.read()==1 ? "true" : "false") << endl;
cout << "Zero flag : " << (zero.read() == 1 ? "true" : "false") << endl;
cout << "Less than : " << (lessFlag.read() == 1 ? "true" : "false") << endl;
cout << endl;
}
void ev_handler()
{
cout << "sc_get_status() == " << hex << sc_get_status() << " METHOD in " << name() << endl;
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sig.read() == 42 );
static bool first = true;
if (first)
{
sc_assert( sc_time_stamp() == SC_ZERO_TIME );
first = false;
}
else
sc_assert( sc_time_stamp() == sc_time(42, SC_US) );
}
void T()
{
cout << "sc_get_status() == " << hex << sc_get_status() << " PROCESS in " << name() << endl;
sc_assert( sc_delta_count() == 0 );
sc_assert( sig.read() == 42 );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
wait(timed_ev);
sc_assert( sc_time_stamp() == sc_time(42, SC_US) );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
sc_pause();
cout << "sc_get_status() == " << hex << sc_get_status() << " PROCESS after sc_pause in " << name() << endl;
sc_assert( sc_time_stamp() == sc_time(42, SC_US) );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
wait(SC_ZERO_TIME);
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
sc_pause();
cout << "sc_get_status() == " << hex << sc_get_status() << " PROCESS after sc_pause in " << name() << endl;
sc_assert( sc_time_stamp() == sc_time(42, SC_US) );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
wait(2, SC_US);
sc_assert( sc_time_stamp() == sc_time(44, SC_US) );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
sc_stop();
cout << "sc_get_status() == " << hex << sc_get_status() << " PROCESS after sc_stop() in " << name() << endl;;
sc_assert( sc_time_stamp() == sc_time(44, SC_US) );
sc_assert( sc_get_status() == SC_RUNNING );
sc_assert( sc_is_running() == true );
sc_pause();
sc_assert( sc_get_status() == SC_RUNNING );
}
void T()
{
sc_assert( sig1.read() == 1 );
sc_assert( sig2.read() == 2 );
sc_assert( sig3.read() == 3 );
}
int sc_main(int argc, char* argv[])
{
dma.clk(clk);
dma.rst(rst);
//slave
dma.addr_s(addr_s);
dma.wdata_s(wdata_s);
dma.rdata_s(rdata_s);
dma.rw_s(rw_s);
dma.opreq_s(opreq_s);
dma.opack_s(opack_s);
dma.irq_s(irq_s);
dma.irqClr_s(irqClr_s);
//master
dma.addr_m(addr_m);
dma.wdata_m(wdata_m);
dma.rdata_m(rdata_m);
dma.rw_m(rw_m);
dma.opreq_m(opreq_m);
dma.opack_m(opack_m);
sc_trace_file *tf = sc_create_vcd_trace_file("RESULT");
sc_trace(tf, clk, "clk");
sc_trace(tf, rst, "rst");
sc_trace(tf, addr_s, "addr_s");
sc_trace(tf, wdata_s, "wdata_s");
sc_trace(tf, rdata_s, "rdata_s");
sc_trace(tf, rw_s, "rw_s");
sc_trace(tf, opreq_s, "opreq_s");
sc_trace(tf, opack_s, "opack_s");
sc_trace(tf, irq_s, "irq_s");
sc_trace(tf, irqClr_s, "irqClr_s");
sc_trace(tf, addr_m, "addr_m");
sc_trace(tf, wdata_m, "wdata_m");
sc_trace(tf, rdata_m, "rdata_m");
sc_trace(tf, rw_m, "rw_m");
sc_trace(tf, opreq_m, "opreq_m");
sc_trace(tf, opack_m, "opack_m");
rst.write(1);
sc_start(clkPrd);
rst.write(0);
sc_start(clkPrd);
irqClr_s.write(0);
rst.write(1);
sc_start(clkPrd);
// ---- write to DMA internal registers ----
//write to register "source"
rwTrasaction(0x0, 0x40000000, 0);
//write to register "target"
rwTrasaction(0x4, 0x20000000, 0);
//write to register "size"
rwTrasaction(0x8, 5, 0);
//write to register "start"
rwTrasaction(0xc, 0xffffffff, 0);
// ---- read the contain of DMA internel registers
//read register "source"
rwTrasaction(0x0, 0, 1);
//read register "target"
rwTrasaction(0x4, 0, 1);
//read register "size"
rwTrasaction(0x8, 0, 1);
//read register "start"
rwTrasaction(0xc, 0, 1);
//DMA is moving data
int i = 0;
sc_start(clkPrd);
while(1) {
if (opreq_m.read()) {
//DMA read data from memory
if ( rw_m.read() ) {
rdata_m.write(i++);
opack_m.write(1);
sc_start(clkPrd);
opack_m.write(0);
} else { // DMA write data to memory
sc_start(clkPrd*2); //set writing memory need 2 clock
opack_m.write(1);
sc_start(clkPrd);
opack_m.write(0);
}
} else {
opack_m.write(0);
sc_start(clkPrd);
}
if (irq_s == 1) break;
}
irqClr_s.write(1);
sc_start(clkPrd * 20);
sc_close_vcd_trace_file(tf);
return 0;
}
