void xImpl_IncDec::operator()( const xRegisterInt& to ) const
{
if( to.Is8BitOp() )
{
xWrite8( 0xfe );
EmitSibMagic( isDec ? 1 : 0, to );
}
else
{
to.prefix16();
xWrite8( (isDec ? 0x48 : 0x40) | to.Id );
}
}
void xImpl_Test::operator()( const xRegisterInt& to, int imm ) const
{
to.prefix16();
if( to.IsAccumulator() )
xWrite8( to.Is8BitOp() ? 0xa8 : 0xa9 );
else
{
xWrite8( to.Is8BitOp() ? 0xf6 : 0xf7 );
EmitSibMagic( 0, to );
}
to.xWriteImm( imm );
}
void xImpl_IncDec::operator()(const xRegisterInt &to) const
{
if (to.Is8BitOp()) {
u8 regfield = isDec ? 1 : 0;
xOpWrite(to.GetPrefix16(), 0xfe, regfield, to);
} else {
#ifdef __x86_64__
pxAssertMsg(0, "Single Byte INC/DEC aren't valid in 64 bits."
"You need to use the ModR/M form (FF/0 FF/1 opcodes)");
#endif
to.prefix16();
xWrite8((isDec ? 0x48 : 0x40) | to.Id);
}
}
static void _imul_ImmStyle( const xRegisterInt& param1, const SrcType& param2, int imm )
{
// for iMul OpSize is allowed to be 16 or 32 bit only.
const uint OpSize = param1.GetOperandSize();
pxAssert( OpSize == param2.GetOperandSize() );
pxAssert( OpSize > 1 );
xOpWrite0F( (OpSize == 2) ? 0x66 : 0, is_s8( imm ) ? 0x6b : 0x69, param1, param2 );
if( is_s8( imm ) )
xWrite8( (u8)imm );
else
param1.xWriteImm( imm );
}
void xImpl_Group2::operator()(const xRegisterInt& to, u8 imm ) const
{
if( imm == 0 ) return;
to.prefix16();
if( imm == 1 )
{
// special encoding of 1's
xWrite8( to.Is8BitOp() ? 0xd0 : 0xd1 );
EmitSibMagic( InstType, to );
}
else
{
xWrite8( to.Is8BitOp() ? 0xc0 : 0xc1 );
EmitSibMagic( InstType, to );
xWrite8( imm );
}
}
void xImpl_Test::operator()( const xRegisterInt& to, int imm ) const
{
if( to.IsAccumulator() ) {
xOpAccWrite( to.GetPrefix16(), to.Is8BitOp() ? 0xa8 : 0xa9, 0, to );
} else {
xOpWrite( to.GetPrefix16(), to.Is8BitOp() ? 0xf6 : 0xf7, 0, to );
}
to.xWriteImm( imm );
}
static void _g1_EmitOp( G1Type InstType, const xRegisterInt& to, int imm )
{
to.prefix16();
if( !to.Is8BitOp() && is_s8( imm ) )
{
xWrite8( 0x83 );
EmitSibMagic( InstType, to );
xWrite<s8>( imm );
}
else
{
if( to.IsAccumulator() )
xWrite8( (to.Is8BitOp() ? 4 : 5) | (InstType<<3) );
else
{
xWrite8( to.Is8BitOp() ? 0x80 : 0x81 );
EmitSibMagic( InstType, to );
}
to.xWriteImm( imm );
}
}
static void _g1_EmitOp( G1Type InstType, const xRegisterInt& to, const xIndirectVoid& sibsrc )
{
to.prefix16();
xWrite8( (to.Is8BitOp() ? 2 : 3) | (InstType<<3) );
EmitSibMagic( to, sibsrc );
}
static void _g1_EmitOp( G1Type InstType, const xIndirectVoid& sibdest, const xRegisterInt& from )
{
from.prefix16();
xWrite8( (from.Is8BitOp() ? 0 : 1) | (InstType<<3) );
EmitSibMagic( from, sibdest );
}
static void _g3_EmitOp( G3Type InstType, const xRegisterInt& from )
{
from.prefix16();
xWrite8(from.Is8BitOp() ? 0xf6 : 0xf7 );
EmitSibMagic( InstType, from );
}
void xImpl_Group2::operator()( const xRegisterInt& to, const xRegisterCL& /* from */ ) const
{
to.prefix16();
xWrite8( to.Is8BitOp() ? 0xd2 : 0xd3 );
EmitSibMagic( InstType, to );
}
// =====================================================================================================
// TEST / INC / DEC
// =====================================================================================================
void xImpl_Test::operator()( const xRegisterInt& to, const xRegisterInt& from ) const
{
pxAssert( to.GetOperandSize() == from.GetOperandSize() );
xOpWrite( to.GetPrefix16(), to.Is8BitOp() ? 0x84 : 0x85, from, to );
}