void adcifa_calibrate_offset(volatile avr32_adcifa_t *adcifa,
adcifa_opt_t *p_adcifa_opt, uint32_t pb_hz){
/* Sequencer Configuration */
adcifa_sequencer_opt_t adcifa_sequence_opt;
adcifa_sequencer_conversion_opt_t
adcifa_sequence_conversion_opt[CALIBRATION_ADCIFA_NUMBER_OF_SEQUENCE];
/* Configure the ADC */
p_adcifa_opt->sample_and_hold_disable = true;
p_adcifa_opt->single_sequencer_mode = true;
p_adcifa_opt->free_running_mode_enable = false;
p_adcifa_opt->sleep_mode_enable = false;
p_adcifa_opt->mux_settle_more_time = false;
/* Clear offset calibration value before starting calibration */
p_adcifa_opt->offset_calibration_value = 0;
/* Configure ADCIFA core */
adcifa_configure(&AVR32_ADCIFA, p_adcifa_opt, pb_hz);
/* ADCIFA sequencer 0 configuration structure*/
adcifa_sequence_opt.convnb =
CALIBRATION_ADCIFA_NUMBER_OF_SEQUENCE;
adcifa_sequence_opt.resolution =
ADCIFA_SRES_12B;
adcifa_sequence_opt.trigger_selection =
ADCIFA_TRGSEL_SOFT;
adcifa_sequence_opt.start_of_conversion =
ADCIFA_SOCB_ALLSEQ;
adcifa_sequence_opt.sh_mode =
ADCIFA_SH_MODE_OVERSAMP;
adcifa_sequence_opt.half_word_adjustment =
ADCIFA_HWLA_NOADJ;
adcifa_sequence_opt.software_acknowledge =
ADCIFA_SA_NO_EOS_SOFTACK;
/* ADCIFA conversions for sequencer 0*/
for (uint8_t i=0; i<CALIBRATION_ADCIFA_NUMBER_OF_SEQUENCE; i++){
adcifa_sequence_conversion_opt[i].channel_p = AVR32_ADCIFA_INP_GNDANA;
adcifa_sequence_conversion_opt[i].channel_n = AVR32_ADCIFA_INN_GNDANA;
adcifa_sequence_conversion_opt[i].gain = ADCIFA_SHG_1;
}
/* Configure ADCIFA sequencer 0 */
adcifa_configure_sequencer(&AVR32_ADCIFA, 0, &adcifa_sequence_opt,
adcifa_sequence_conversion_opt);
/* Start ADCIFA sequencer 0 */
adcifa_start_sequencer(&AVR32_ADCIFA, 0);
/* Wait end of ADCIFA sequencer 0*/
while(!ADCIFA_is_eos_sequencer_0());
/* The last converted value is the offset value */
p_adcifa_opt->offset_calibration_value =
- ADCIFA_read_resx_sequencer_0(CALIBRATION_ADCIFA_NUMBER_OF_SEQUENCE-1);
}
bool adcifa_check_eos(volatile avr32_adcifa_t * adcifa, U8 sequencer)
{
// Sanity Check
Assert( adcifa!=NULL );
// get SR register : EOS bit for channel
switch (sequencer) {
case 0:
return ((ADCIFA_is_eos_sequencer_0()) ? true : false);
case 1:
return ((ADCIFA_is_eos_sequencer_1()) ? true : false);
default:
break;
}
return false;
}
