static void exynos_adc_v2_exit_hw(struct exynos_adc *info) { u32 con; if (info->data->needs_adc_phy) regmap_write(info->pmu_map, info->data->phy_offset, 0); con = readl(ADC_V2_CON1(info->regs)); con &= ~ADC_CON_EN_START; writel(con, ADC_V2_CON1(info->regs)); }
static void exynos_adc_v2_exit_hw(struct exynos_adc *info) { u32 con; if (info->data->needs_adc_phy) writel(0, info->enable_reg); con = readl(ADC_V2_CON1(info->regs)); con &= ~ADC_CON_EN_START; writel(con, ADC_V2_CON1(info->regs)); }
static void exynos_adc_v2_start_conv(struct exynos_adc *info, unsigned long addr) { u32 con1, con2; con2 = readl(ADC_V2_CON2(info->regs)); con2 &= ~ADC_V2_CON2_ACH_MASK; con2 |= ADC_V2_CON2_ACH_SEL(addr); writel(con2, ADC_V2_CON2(info->regs)); con1 = readl(ADC_V2_CON1(info->regs)); writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs)); }
static void exynos_adc_v2_init_hw(struct exynos_adc *info) { u32 con1, con2; if (info->data->needs_adc_phy) regmap_write(info->pmu_map, info->data->phy_offset, 1); con1 = ADC_V2_CON1_SOFT_RESET; writel(con1, ADC_V2_CON1(info->regs)); con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); writel(con2, ADC_V2_CON2(info->regs)); /* Enable interrupts */ writel(1, ADC_V2_INT_EN(info->regs)); }