void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
post_code(0x31);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x39);
AGESAWRAPPER(amdinitearly);
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
AGESAWRAPPER(amdinitpost);
post_code(0x41);
AGESAWRAPPER(amdinitenv);
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
AGESAWRAPPER(amdinitresume);
AGESAWRAPPER(amds3laterestore);
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
post_code(0x30);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
post_code(0x31);
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);
post_code(0x35);
console_init();
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x38);
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
post_code(0x39);
nb_Poweron_Init();
post_code(0x3A);
sb_Poweron_Init();
}
post_code(0x3B);
AGESAWRAPPER(amdinitearly);
post_code(0x3C);
nb_Ht_Init();
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x40);
AGESAWRAPPER(amdinitpost);
post_code(0x41);
AGESAWRAPPER(amdinitenv);
post_code(0x42);
post_code(0x50);
print_debug("Disabling cache as ram ");
disable_cache_as_ram();
print_debug("done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
print_debug("should not be here -\n");
post_code(0x54);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
#if CONFIG_SVI2_SLOW_SPEED
device_t d18f3_dev = PCI_DEV(0, 0x18, 3);
#endif //CONFIG_SVI2_SLOW_SPEED
#if CONFIG_SVI_WAIT_COMP_DIS
device_t d18f5_dev = PCI_DEV(0, 0x18, 5);
#endif //CONFIG_SVI_WAIT_COMP_DIS
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
* replicated in every reference design since Parmer, so it is
* believed to be required even though it is not documented in
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
if (!cpu_init_detectedx && boot_cpu()) {
u32 data, *memptr;
hudson_lpc_port80();
//
// Configure the GPIO's
//
HandleFchGpioTbl ( (GPIO_CONTROL *) &gGpioInitTable[0] );
hudson_clk_output_48Mhz();
post_code(0x31);
console_init();
printk(BIOS_INFO, "14-25-48Mhz Clock settings\n");
memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28 );
data = *memptr;
printk(BIOS_INFO, "FCH_MISC_REG28 is 0x%08x \n", data);
memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
data = *memptr;
printk(BIOS_INFO, "FCH_MISC_REG40 is 0x%08x \n", data);
//
// Configure clock request
//
data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00));
data &= 0xFFFF0000;
data |= (0 + 1) << (0 * 4); // CLKREQ 0 to CLK0
data |= (1 + 1) << (1 * 4); // CLKREQ 1 to CLK1
data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2
data |= (3 + 1) << (3 * 4); // CLKREQ 3 to CLK3
*((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)) = data;
data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04));
data &= 0xFFFFFF0F;
data |= 0xA << (1 * 4); // CLKREQ GFX to GFXCLK
*((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data;
// //
// // Configure clock strength
// //
// data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24));
//
// data &= ~( (3 << 18) | (3 << 6) | (3 << 4) | (3 << 2) | (3 << 0) );
// data |= 3 << 18; // GFX CLOCK
// data |= 3 << (0 * 2); // CLK0
// data |= 3 << (1 * 2); // CLK1
// data |= 3 << (2 * 2); // CLK2
// data |= 3 << (3 * 2); // CLK3
//
// *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)) = data;
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/*
* This refers to LpcClkDrvSth settling time. Without this setting, processor
* initialization is slow or incorrect, so this wait has been replicated from
* earlier development boards.
*/
{ int i; for(i = 0; i < 200000; i++) inb(0xCD6); }
post_code(0x37);
AGESAWRAPPER(amdinitreset);
/* TODO There is no debug output between the return from amdinitreset and amdinitearly */
post_code(0x38);
printk(BIOS_DEBUG, "Got past avalon_early_setup\n");
post_code(0x39);
AGESAWRAPPER(amdinitearly);
/*
// Moved here to prevent double signon message
// amdinitreset AGESA code might issue a reset when the hardware is in a wrong state.
*/
printk(BIOS_ERR, CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ERR, "coreboot build " COREBOOT_YYYYMMDD_DATE "\n");
#if CONFIG_SVI2_SLOW_SPEED
/* Force SVI2 to slow speed for APU2 */
val = pci_read_config32( d18f3_dev, 0xA0);
if ( val & (1 << 14 ) ) {
printk(BIOS_DEBUG, "SVI2 FREQUENCY 20 Mhz changing to 3.4\n");
val &= ~(1 << 14 );
pci_write_config32(d18f3_dev, 0xA0, val );
} else {
printk(BIOS_DEBUG, "SVI2 FREQUENCY 3.4 Mhz\n");
}
#endif //CONFIG_SVI2_SLOW_SPEED
#if CONFIG_SVI_WAIT_COMP_DIS
/* Disable SVI2 controller to wait for command completion */
val = pci_read_config32( d18f5_dev, 0x12C);
if ( val & (1 << 30 ) ) {
printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
} else {
printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
val |= (1 << 30 );
pci_write_config32(d18f5_dev, 0x12C, val );
}
#endif //CONFIG_SVI_WAIT_COMP_DIS
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
AGESAWRAPPER(amdinitpost);
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
/*
If code hangs here, please check cahaltasm.S
*/
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
AGESAWRAPPER(amdinitresume);
AGESAWRAPPER(amds3laterestore);
post_code(0x61);
prepare_for_resume();
}
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
