// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fcc_eth_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *)0;
volatile t_EnetFcc_Pram *E_fcc;
int i, fcc_chan;
bool esa_ok;
unsigned char *c_ptr;
unsigned char _enaddr[6];
unsigned long rxbase, txbase;
struct fcc_bd *rxbd, *txbd;
// The FCC seems rather picky about these...
static long rxbd_base = 0x3000;
static long txbd_base = 0xB000;
#ifdef CYGPKG_DEVS_ETH_PHY
unsigned short phy_state = 0;
#endif
// Set up pointers to FCC controller
switch (qi->int_vector) {
case CYGNUM_HAL_INTERRUPT_FCC1:
qi->fcc_reg = &(IMM->fcc_regs[FCC1]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC1_PRAM_OFFSET);
fcc_chan = FCC1_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC2:
qi->fcc_reg = &(IMM->fcc_regs[FCC2]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC2_PRAM_OFFSET);
fcc_chan = FCC2_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC3:
qi->fcc_reg = &(IMM->fcc_regs[FCC3]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC3_PRAM_OFFSET);
fcc_chan = FCC3_PAGE_SUBBLOCK;
break;
default:
os_printf("Can't initialize '%s' - unknown FCC!\n", dtp->name);
return false;
}
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
// No 'flash config' data available - use default
os_printf("FCC_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
// Initialize Receive Buffer Descriptors
rxbase = rxbd_base;
fcc->riptr = rxbase; // temp work buffer
fcc->mrblr = FCC_PRAM_MRBLR; // Max Rx buffer
fcc->rstate &= FCC_FCR_INIT;
fcc->rstate |= FCC_FCR_MOT_BO;
rxbase += 64;
rxbd_base += sizeof(struct fcc_bd)*qi->rxnum + 64;
rxbd = (struct fcc_bd *)(CYGARC_IMM_BASE + rxbase);
fcc->rbase = (CYG_WORD)rxbd;
c_ptr = qi->rxbuf;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
for (i = 0; i < qi->rxnum; i++, rxbd++) {
rxbd->ctrl = (FCC_BD_Rx_Empty | FCC_BD_Rx_Int);
rxbd->length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
rxbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
rxbd--;
rxbd->ctrl |= FCC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
txbase = txbd_base;
fcc->tiptr = txbase; // in dual port RAM (see 28-11)
fcc->tstate &= FCC_FCR_INIT;
fcc->tstate |= FCC_FCR_MOT_BO;
txbase += 64;
txbd_base += sizeof(struct fcc_bd)*qi->txnum + 64;
txbd = (struct fcc_bd *)(CYGARC_IMM_BASE + txbase);
fcc->tbase = (CYG_WORD)txbd;
c_ptr = qi->txbuf;
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
for (i = 0; i < qi->txnum; i++, txbd++) {
txbd->ctrl = (FCC_BD_Tx_Pad | FCC_BD_Tx_Int);
txbd->length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
txbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
txbd--;
txbd->ctrl |= FCC_BD_Tx_Wrap;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc = &(fcc->SpecificProtocol.e);
E_fcc->c_mask = FCC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FCC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FCC_PRAM_RETLIM;
E_fcc->p_per = FCC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FCC_MAX_FLR;
E_fcc->paddr1_h = ((short)qi->enaddr[5] << 8) | qi->enaddr[4];
E_fcc->paddr1_m = ((short)qi->enaddr[3] << 8) | qi->enaddr[2];
E_fcc->paddr1_l = ((short)qi->enaddr[1] << 8) | qi->enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FCC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = fcc->tiptr; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FCC_PRAM_MAXD;
E_fcc->maxd2 = FCC_PRAM_MAXD;
// FCC register initialization
qi->fcc_reg->fcc_gfmr = FCC_GFMR_INIT;
qi->fcc_reg->fcc_psmr = FCC_PSMR_INIT;
qi->fcc_reg->fcc_dsr = FCC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCCX
qi->fcc_reg->fcc_fcce = 0xFFFF;
qi->fcc_reg->fcc_fccm = FCC_EV_TXE | FCC_EV_TXB | FCC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fcc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->fcc_eth_interrupt_handle,
&qi->fcc_eth_interrupt);
cyg_drv_interrupt_attach(qi->fcc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#else
// Mask the interrupts
qi->fcc_reg->fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCCx
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
fcc_chan |
CPCR_MCN_FCC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Operating mode
if (!_eth_phy_init(qi->phy)) {
return false;
}
#ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
_eth_phy_reset(qi->phy);
#endif
phy_state = _eth_phy_state(qi->phy);
os_printf("FCC %s: ", sc->dev_name);
if ((phy_state & ETH_PHY_STAT_LINK) != 0) {
if ((phy_state & ETH_PHY_STAT_100MB) != 0) {
// Link can handle 100Mb
os_printf("100Mb");
if ((phy_state & ETH_PHY_STAT_FDX) != 0) {
os_printf("/Full Duplex");
}
} else {
// Assume 10Mb, half duplex
os_printf("10Mb");
}
} else {
os_printf("/***NO LINK***\n");
#ifdef CYGPKG_REDBOOT
return false;
#endif
}
os_printf("\n");
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
volatile t_BCSR *CSR = (t_BCSR *) 0x04500000;
#endif
int i;
bool esa_ok;
bool fec_100;
unsigned char *c_ptr;
UINT16 link_speed;
// Link the memory to the driver control memory
qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
// Via BCSR, (re)start LXT970
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
EnableResetPHY(CSR);
#endif
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_100", &fec_100, CONFIG_BOOL);
#endif
link_speed = NOTLINKED;
if(esa_ok && fec_100){
// Via MII Management pins, tell LXT970 to initialize
os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
HUNDRED_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
os_printf("Failed to get 100 Mbps half_duplex link.\n");
}
}
if(link_speed == NOTLINKED){
os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
TEN_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
link_speed = LinkTestPHY();
os_printf("Failed to get 10 Mbps half_duplex link.\n");
}
}
switch ( link_speed ) {
case HUNDRED_FD:
os_printf("100 MB full-duplex ethernet link \n");
break;
case HUNDRED_HD:
os_printf("100 MB half-duplex ethernet link \n");
break;
case TEN_FD:
os_printf("10 MB full-duplex ethernet link \n");
break;
case TEN_HD:
os_printf("10 MB half-duplex ethernet link \n");
break;
default:
os_printf("NO ethernet link \n");
}
// Connect PORTC pins: (C19) to clk13, (C18) to clk 14
IMM->io_regs[PORT_C].ppar |= 0x00003000;
IMM->io_regs[PORT_C].podr &= ~(0x00003000);
IMM->io_regs[PORT_C].psor &= ~(0x00003000);
IMM->io_regs[PORT_C].pdir &= ~(0x00003000);
// Connect clk13 to RxClk and clk14 to TxClk on FCC2
IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14)
IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear
// Initialize parallel port registers to connect FCC2 to MII
IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31
IMM->io_regs[PORT_B].psor &= 0xffffc000;
IMM->io_regs[PORT_B].pdir &= 0xffffc000;
IMM->io_regs[PORT_B].psor |= 0x00000004;
IMM->io_regs[PORT_B].pdir |= 0x000003c5;
IMM->io_regs[PORT_B].ppar |= 0x00003fff;
// Initialize Receive Buffer Descriptors
qi->rbase = fec_eth_rxring;
qi->rxbd = fec_eth_rxring;
qi->rnext = fec_eth_rxring;
c_ptr = fec_eth_rxbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
fec_eth_rxring[i].length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
qi->tbase = fec_eth_txring;
qi->txbd = fec_eth_txring;
qi->tnext = fec_eth_txring;
c_ptr = fec_eth_txbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);
fec_eth_txring[i].length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
// Common FCC Parameter RAM initialization
fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11)
fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11)
fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ...
fcc->rstate &= FEC_FCR_INIT;
fcc->rstate |= FEC_FCR_MOT_BO;
fcc->rbase = (long) fec_eth_rxring;
fcc->tstate &= FEC_FCR_INIT;
fcc->tstate |= FEC_FCR_MOT_BO;
fcc->tbase = (long) fec_eth_txring;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FEC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FEC_PRAM_RETLIM;
E_fcc->p_per = FEC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FEC_MAX_FLR;
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// If can't use the default ...
os_printf("FEC_ETH - Warning! ESA unknown\n");
memcpy(enaddr, _default_enaddr, sizeof(enaddr));
}
E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2];
E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FEC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FEC_PRAM_MAXD;
E_fcc->maxd2 = FEC_PRAM_MAXD;
// FCC register initialization
IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT;
IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT;
IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCC2
IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000;
IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(FEC_ETH_INT,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fec_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&fec_eth_interrupt_handle,
&fec_eth_interrupt);
cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#else
// Mask the interrupts
IMM->fcc_regs[FCC2].fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCC2
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
CPCR_FCC2_CH |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
