INLINE void execute_one(int opcode)
{
i8085_ICount -= I.cputype ? i8085_lut_cycles_8085[opcode] : i8085_lut_cycles_8080[opcode];
switch (opcode)
{
case 0x00: /* NOP */
/* no op */
break;
case 0x01: /* LXI B,nnnn */
I.BC.w.l = ARG16();
break;
case 0x02: /* STAX B */
WM(I.BC.d, I.AF.b.h);
break;
case 0x03: /* INX B */
I.BC.w.l++;
if( I.cputype ) { if (I.BC.w.l == 0x0000) I.AF.b.l |= X5F; else I.AF.b.l &= ~X5F; }
break;
case 0x04: /* INR B */
M_INR(I.BC.b.h);
break;
case 0x05: /* DCR B */
M_DCR(I.BC.b.h);
break;
case 0x06: /* MVI B,nn */
M_MVI(I.BC.b.h);
break;
case 0x07: /* RLC */
M_RLC;
break;
case 0x08:
if( I.cputype ) {
/* DSUB */
M_DSUB();
} else {
/* NOP undocumented */
}
break;
case 0x09: /* DAD B */
M_DAD(BC);
break;
case 0x0a: /* LDAX B */
I.AF.b.h = RM(I.BC.d);
break;
case 0x0b: /* DCX B */
I.BC.w.l--;
if( I.cputype ) { if (I.BC.w.l == 0xffff) I.AF.b.l |= X5F; else I.AF.b.l &= ~X5F; }
break;
case 0x0c: /* INR C */
M_INR(I.BC.b.l);
break;
case 0x0d: /* DCR C */
M_DCR(I.BC.b.l);
break;
case 0x0e: /* MVI C,nn */
M_MVI(I.BC.b.l);
break;
case 0x0f: /* RRC */
M_RRC;
break;
case 0x10:
if( I.cputype ) {
/* ASRH */
I.AF.b.l = (I.AF.b.l & ~CF) | (I.HL.b.l & CF);
I.HL.w.l = (I.HL.w.l >> 1);
} else {
/* NOP undocumented */
}
break;
/**********************************************************
* main opcodes
**********************************************************/
OP(op,00) { } /* NOP */
OP(op,01) { cpustate->_BC = ARG16(cpustate); } /* LD BC,w */
OP(op,02) { WM(cpustate, cpustate->_BC, cpustate->_A ); } /* LD (BC),A */
OP(op,03) { cpustate->_BC++; } /* INC BC */
OP(op,04) { cpustate->_B = INC(cpustate, cpustate->_B); } /* INC B */
OP(op,05) { cpustate->_B = DEC(cpustate, cpustate->_B); } /* DEC B */
OP(op,06) { cpustate->_B = ARG(cpustate); } /* LD B,n */
OP(op,07) { RLCA; } /* RLCA */
OP(op,08) { EX_AF; } /* EX AF,AF' */
OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */
OP(op,0a) { cpustate->_A = RM(cpustate, cpustate->_BC); } /* LD A,(BC) */
OP(op,0b) { cpustate->_BC--; } /* DEC BC */
OP(op,0c) { cpustate->_C = INC(cpustate, cpustate->_C); } /* INC C */
OP(op,0d) { cpustate->_C = DEC(cpustate, cpustate->_C); } /* DEC C */
OP(op,0e) { cpustate->_C = ARG(cpustate); } /* LD C,n */
OP(op,0f) { RRCA; } /* RRCA */
OP(op,10) { cpustate->_B--; JR_COND( cpustate->_B, 0x10 ); } /* DJNZ o */
OP(op,11) { cpustate->_DE = ARG16(cpustate); } /* LD DE,w */
OP(op,12) { WM(cpustate, cpustate->_DE, cpustate->_A ); } /* LD (DE),A */
OP(op,13) { cpustate->_DE++; } /* INC DE */
OP(op,14) { cpustate->_D = INC(cpustate, cpustate->_D); } /* INC D */
OP(op,15) { cpustate->_D = DEC(cpustate, cpustate->_D); } /* DEC D */
OP(op,16) { cpustate->_D = ARG(cpustate); } /* LD D,n */
OP(op,17) { RLA; } /* RLA */
} \
}
#else
#define CHECK_BC_LOOP
#define CHECK_DE_LOOP
#define CHECK_HL_LOOP
#endif
/**********************************************************
* main opcodes
**********************************************************/
OP(op,00) { } /* NOP */
OP(op,01) { _BC = ARG16(); } /* LD BC,w */
OP(op,02) { WM( _BC, _A ); } /* LD (BC),A */
OP(op,03) { _BC++; } /* INC BC */
OP(op,04) { _B = INC(_B); } /* INC B */
OP(op,05) { _B = DEC(_B); } /* DEC B */
OP(op,06) { _B = ARG(); } /* LD B,n */
OP(op,07) { RLCA; } /* RLCA */
OP(op,08) { EX_AF; } /* EX AF,AF' */
OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */
OP(op,0a) { _A = RM(_BC); } /* LD A,(BC) */
OP(op,0b) { _BC--; CHECK_BC_LOOP; } /* DEC BC */
OP(op,0c) { _C = INC(_C); } /* INC C */
OP(op,0d) { _C = DEC(_C); } /* DEC C */
OP(op,0e) { _C = ARG(); } /* LD C,n */
OP(op,0f) { RRCA; } /* RRCA */
