/* a fiber pends on a semaphore then times out */
static void test_fiber_pend_and_timeout(int data, int unused)
{
struct timeout_order_data *the_data = (void *)data;
int32_t orig_ticks = sys_tick_get();
int rv;
ARG_UNUSED(unused);
rv = nano_fiber_sem_take(the_data->sem, the_data->timeout);
if (rv) {
TC_ERROR(" *** timeout of %d did not time out.\n",
the_data->timeout);
return;
}
if (!is_timeout_in_range(orig_ticks, the_data->timeout)) {
return;
}
nano_fiber_fifo_put(&timeout_order_fifo, the_data);
}
static int stm32_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
u32_t *rate)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
/*
* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
* since it will be updated after clock configuration and hence
* more likely to contain actual clock speed
*/
u32_t ahb_clock = SystemCoreClock;
u32_t apb1_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB1_PRESCALER);
#ifndef CONFIG_SOC_SERIES_STM32F0X
u32_t apb2_clock = get_bus_clock(ahb_clock,
CONFIG_CLOCK_STM32_APB2_PRESCALER);
#endif /* CONFIG_SOC_SERIES_STM32F0X */
ARG_UNUSED(clock);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
case STM32_CLOCK_BUS_AHB2:
*rate = ahb_clock;
break;
case STM32_CLOCK_BUS_APB1:
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB1_2:
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
*rate = apb1_clock;
break;
#ifndef CONFIG_SOC_SERIES_STM32F0X
case STM32_CLOCK_BUS_APB2:
*rate = apb2_clock;
break;
#endif /* CONFIG_SOC_SERIES_STM32F0X */
}
return 0;
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam3x_init(struct device *arg)
{
u32_t key;
ARG_UNUSED(arg);
/* Note:
* Magic numbers below are obtained by reading the registers
* when the SoC was running the SAM-BA bootloader
* (with reserved bits set to 0).
*/
key = irq_lock();
/* Setup the flash controller.
* The bootloader is running @ 48 MHz with
* FWS == 2.
* When running at 84 MHz, FWS == 4 seems
* to be more stable, and allows the board
* to boot.
*/
__EEFC0->fmr = 0x00000400;
__EEFC1->fmr = 0x00000400;
_ClearFaults();
/* Setup master clock */
clock_init();
/* Disable watchdog timer, not used by system */
__WDT->mr |= WDT_DISABLE;
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
static int qdec_nrfx_sample_fetch(struct device *dev, enum sensor_channel chan)
{
struct qdec_nrfx_data *data = &qdec_nrfx_data;
int16_t acc;
int16_t accdbl;
ARG_UNUSED(dev);
LOG_DBG("");
if ((chan != SENSOR_CHAN_ALL) && (chan != SENSOR_CHAN_ROTATION)) {
return -ENOTSUP;
}
nrfx_qdec_accumulators_read(&acc, &accdbl);
accumulate(data, acc);
return 0;
}
static int pinmux_set(struct device *dev, uint32_t pin, uint32_t func)
{
volatile struct __pio *port = _get_port(pin);
uint32_t tmp;
ARG_UNUSED(dev);
if (!port) {
return -EINVAL;
}
tmp = port->absr;
if (func) {
tmp |= (1 << (pin % 32));
} else {
tmp &= ~(1 << (pin % 32));
}
port->absr = tmp;
return 0;
}
/* Interrupt handler, gets messages on all incoming enabled mailboxes */
void quark_se_ipm_isr(void *param)
{
int channel;
int sts, bit;
struct device *d;
struct quark_se_ipm_config_info *config;
struct quark_se_ipm_driver_data *driver_data;
volatile struct quark_se_ipm *ipm;
unsigned int key;
ARG_UNUSED(param);
sts = quark_se_ipm_sts_get();
__ASSERT(sts, "spurious IPM interrupt");
bit = find_msb_set(sts) - 1;
channel = bit / 2;
d = device_by_channel[channel];
__ASSERT(d, "got IRQ on channel with no IPM device");
config = d->config->config_info;
driver_data = d->driver_data;
ipm = config->ipm;
__ASSERT(driver_data->callback, "enabled IPM channel with no callback");
driver_data->callback(driver_data->callback_ctx, ipm->ctrl.ctrl,
&ipm->data);
key = irq_lock();
ipm->sts.irq = 1; /* Clear the interrupt bit */
ipm->sts.sts = 1; /* Clear channel status bit */
/* Wait for the above register writes to clear the channel
* to propagate to the global channel status register
*/
while (quark_se_ipm_sts_get() & (0x3 << (channel * 2))) {
/* Busy-wait */
}
irq_unlock(key);
}
static void recv_cb(struct net_context *net_ctx, struct net_pkt *pkt,
int status, void *data)
{
struct http_client_ctx *ctx = data;
ARG_UNUSED(net_ctx);
if (status) {
return;
}
if (!pkt || net_pkt_appdatalen(pkt) == 0) {
/*
* This block most likely handles a TCP_FIN message.
* (this means the connection is now closed)
* If we get here, and req.wait.count is still 0 this means
* http client is still waiting to parse a response body.
* This will will never happen now. Instead of generating
* an ETIMEDOUT error in the future, let's unlock the
* req.wait semaphore and let the app deal with whatever
* data was parsed in the header (IE: http status, etc).
*/
if (ctx->req.wait.count == 0) {
k_sem_give(&ctx->req.wait);
}
goto out;
}
/* receive_cb must take ownership of the received packet */
if (ctx->tcp.receive_cb) {
ctx->tcp.receive_cb(ctx, pkt);
return;
}
out:
if (pkt) {
net_pkt_unref(pkt);
}
}
/**
*
* @brief Stack test fiber
*
* @param par1 Ignored parameter.
* @param par2 Number of test loops.
*
* @return N/A
*
*/
void stack_fiber1(int par1, int par2)
{
int i;
uint32_t data;
ARG_UNUSED(par1);
for (i = 0; i < par2 / 2; i++) {
nano_fiber_stack_pop(&nano_stack_1, &data, TICKS_UNLIMITED);
if (data != 2 * i) {
break;
}
data = 2 * i;
nano_fiber_stack_push(&nano_stack_2, data);
nano_fiber_stack_pop(&nano_stack_1, &data, TICKS_UNLIMITED);
if (data != 2 * i + 1) {
break;
}
data = 2 * i + 1;
nano_fiber_stack_push(&nano_stack_2, data);
}
}
static void hpet_isr(void *arg)
{
ARG_UNUSED(arg);
k_spinlock_key_t key = k_spin_lock(&lock);
u32_t now = MAIN_COUNTER_REG;
u32_t dticks = (now - last_count) / cyc_per_tick;
last_count += dticks * cyc_per_tick;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL) ||
IS_ENABLED(CONFIG_QEMU_TICKLESS_WORKAROUND)) {
u32_t next = last_count + cyc_per_tick;
if ((s32_t)(next - now) < MIN_DELAY) {
next += cyc_per_tick;
}
TIMER0_COMPARATOR_REG = next;
}
k_spin_unlock(&lock, key);
z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
}
static void fiberEntry(int task_thread_id, int arg1)
{
int rv;
ARG_UNUSED(arg1);
fiberEvidence++; /* Prove to the task that the fiber has run */
nano_fiber_sem_take(&wakeFiber, TICKS_UNLIMITED);
rv = nanoCtxFiberTest((nano_thread_id_t) task_thread_id);
if (rv != TC_PASS) {
return;
}
/* Allow the task to print any messages before the next test runs */
nano_fiber_sem_take(&wakeFiber, TICKS_UNLIMITED);
rv = fiber_yieldTest();
if (rv != TC_PASS) {
return;
}
}
void isr_rand(void *param)
{
ARG_UNUSED(param);
if (NRF_RNG->EVENTS_VALRDY) {
u8_t last;
last = rng->last + 1;
if (last == rng->count) {
last = 0;
}
if (last == rng->first) {
/* this condition should not happen
* , but due to probable bug in HW
* , new value could be generated
* before task is stopped.
*/
NRF_RNG->TASKS_STOP = 1;
NRF_RNG->EVENTS_VALRDY = 0;
return;
}
rng->rand[rng->last] = NRF_RNG->VALUE;
rng->last = last;
last = rng->last + 1;
if (last == rng->count) {
last = 0;
}
NRF_RNG->EVENTS_VALRDY = 0;
if (last == rng->first) {
NRF_RNG->TASKS_STOP = 1;
}
}
}
int z_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
IRQ_CONNECT(TIMER_IRQ, DT_LITEX_TIMER0_E0002800_IRQ_0_PRIORITY,
litex_timer_irq_handler, NULL, 0);
irq_enable(TIMER_IRQ);
sys_write8(TIMER_DISABLE, TIMER_EN_ADDR);
for (int i = 0; i < 4; i++) {
sys_write8(sys_clock_hw_cycles_per_tick() >> (24 - i * 8),
TIMER_RELOAD_ADDR + i * 0x4);
sys_write8(sys_clock_hw_cycles_per_tick() >> (24 - i * 8),
TIMER_LOAD_ADDR + i * 0x4);
}
sys_write8(TIMER_ENABLE, TIMER_EN_ADDR);
sys_write8(sys_read8(TIMER_EV_PENDING_ADDR), TIMER_EV_PENDING_ADDR);
sys_write8(TIMER_EV, TIMER_EV_ENABLE_ADDR);
return 0;
}
static void isr(void *arg)
{
int byte, ret;
ARG_UNUSED(arg);
byte = random_byte_get();
if (byte < 0) {
return;
}
ret = rng_pool_put((struct rng_pool *)(entropy_nrf5_data.isr), byte);
if (ret < 0) {
ret = rng_pool_put((struct rng_pool *)(entropy_nrf5_data.thr),
byte);
if (ret < 0) {
nrf_rng_task_trigger(NRF_RNG_TASK_STOP);
}
k_sem_give(&entropy_nrf5_data.sem_sync);
}
}
void stack_fiber1(int par1, int par2)
{
int i;
uint32_t data;
ARG_UNUSED(par1);
for (i = 0; i < par2 / 2; i++) {
data = nano_fiber_stack_pop_wait(&nano_stack_1);
if (data != 2 * i) {
break;
}
data = 2 * i;
nano_fiber_stack_push(&nano_stack_2, data);
data = nano_fiber_stack_pop_wait(&nano_stack_1);
if (data != 2 * i + 1) {
break;
}
data = 2 * i + 1;
nano_fiber_stack_push(&nano_stack_2, data);
}
}
static int _bt_spi_init(struct device *unused)
{
ARG_UNUSED(unused);
spi_dev = device_get_binding(CONFIG_BLUETOOTH_SPI_DEV_NAME);
if (!spi_dev) {
BT_ERR("Failed to initialize SPI driver: %s",
CONFIG_BLUETOOTH_SPI_DEV_NAME);
return -EIO;
}
#if defined(CONFIG_BLUETOOTH_SPI_BLUENRG)
cs_dev = device_get_binding(CONFIG_BLUETOOTH_SPI_CHIP_SELECT_DEV_NAME);
if (!cs_dev) {
BT_ERR("Failed to initialize GPIO driver: %s",
CONFIG_BLUETOOTH_SPI_CHIP_SELECT_DEV_NAME);
return -EIO;
}
#endif /* CONFIG_BLUETOOTH_SPI_BLUENRG */
irq_dev = device_get_binding(CONFIG_BLUETOOTH_SPI_IRQ_DEV_NAME);
if (!irq_dev) {
BT_ERR("Failed to initialize GPIO driver: %s",
CONFIG_BLUETOOTH_SPI_IRQ_DEV_NAME);
return -EIO;
}
rst_dev = device_get_binding(CONFIG_BLUETOOTH_SPI_RESET_DEV_NAME);
if (!rst_dev) {
BT_ERR("Failed to initialize GPIO driver: %s",
CONFIG_BLUETOOTH_SPI_RESET_DEV_NAME);
return -EIO;
}
bt_hci_driver_register(&drv);
return 0;
}
static
int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
u32_t *rate)
{
ARG_UNUSED(clock);
u32_t subsys = POINTER_TO_UINT(sub_system);
u32_t prescaler =
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER;
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
u32_t ahb_clock =
get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
prescaler =
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER;
}
*rate = get_apb_clock(ahb_clock, prescaler);
return 0;
}
void _sys_power_save_idle_exit(int32_t ticks)
{
#if defined(CONFIG_SYS_POWER_LOW_POWER_STATE)
/* Some CPU low power states require notification at the ISR
* to allow any operations that needs to be done before kernel
* switches task or processes nested interrupts. This can be
* disabled by calling _sys_soc_pm_idle_exit_notification_disable().
* Alternatively it can be simply ignored if not required.
*/
if (_sys_pm_idle_exit_notify) {
_sys_soc_resume();
}
#endif
#ifdef CONFIG_TICKLESS_IDLE
if ((ticks == K_FOREVER) || ticks >= _sys_idle_threshold_ticks) {
/* Resume normal periodic system timer interrupts */
_timer_idle_exit();
}
#else
ARG_UNUSED(ticks);
#endif /* CONFIG_TICKLESS_IDLE */
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32f1_init(struct device *arg)
{
u32_t key;
ARG_UNUSED(arg);
key = irq_lock();
_ClearFaults();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 8 MHz from HSI */
SystemCoreClock = 8000000;
return 0;
}
/**
*
* @brief Initialize one UART as the console/debug port
*
* @return 0 if successful, otherwise failed.
*/
static int uart_console_init(struct device *arg)
{
ARG_UNUSED(arg);
uart_console_dev = device_get_binding(CONFIG_UART_CONSOLE_ON_DEV_NAME);
#if defined(CONFIG_USB_UART_CONSOLE) && defined(CONFIG_USB_UART_DTR_WAIT)
while (1) {
u32_t dtr = 0;
uart_line_ctrl_get(uart_console_dev, LINE_CTRL_DTR, &dtr);
if (dtr) {
break;
}
}
k_busy_wait(1000000);
#endif
uart_console_hook_install();
return 0;
}
/* Note: this function has public linkage, and MUST have this
* particular name. The platform architecture itself doesn't care,
* but there is a test (tests/kernel/arm_irq_vector_table) that needs
* to find it to it can set it in a custom vector table. Should
* probably better abstract that at some point (e.g. query and reset
* it by pointer at runtime, maybe?) so we don't have this leaky
* symbol.
*/
void rtc1_nrf_isr(void *arg)
{
ARG_UNUSED(arg);
RTC->EVENTS_COMPARE[0] = 0;
u32_t key = irq_lock();
u32_t t = counter();
u32_t dticks = counter_sub(t, last_count) / CYC_PER_TICK;
last_count += dticks * CYC_PER_TICK;
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
u32_t next = last_count + CYC_PER_TICK;
if (counter_sub(next, t) < MIN_DELAY) {
next += CYC_PER_TICK;
}
set_comparator(next);
}
irq_unlock(key);
z_clock_announce(dticks);
}
int net_nbr_unlink(struct net_nbr *nbr, struct net_linkaddr *lladdr)
{
ARG_UNUSED(lladdr);
if (nbr->idx == NET_NBR_LLADDR_UNKNOWN) {
return -EALREADY;
}
NET_ASSERT(nbr->idx < CONFIG_NET_IPV6_MAX_NEIGHBORS);
NET_ASSERT(net_neighbor_lladdr[nbr->idx].ref > 0);
net_neighbor_lladdr[nbr->idx].ref--;
if (!net_neighbor_lladdr[nbr->idx].ref) {
memset(net_neighbor_lladdr[nbr->idx].lladdr.addr, 0,
sizeof(net_neighbor_lladdr[nbr->idx].lladdr.storage));
}
nbr->idx = NET_NBR_LLADDR_UNKNOWN;
nbr->iface = NULL;
return 0;
}
int _sys_clock_driver_init(struct device *device)
{
struct device *clock;
ARG_UNUSED(device);
clock = device_get_binding(CONFIG_CLOCK_CONTROL_NRF5_K32SRC_DRV_NAME);
if (!clock) {
return -1;
}
clock_control_on(clock, (void *)CLOCK_CONTROL_NRF5_K32SRC);
rtc_past = 0;
#ifdef CONFIG_TICKLESS_IDLE
expected_sys_ticks = 1;
#endif /* CONFIG_TICKLESS_IDLE */
/* TODO: replace with counter driver to access RTC */
SYS_CLOCK_RTC->PRESCALER = 0;
nrf_rtc_cc_set(SYS_CLOCK_RTC, RTC_CC_IDX, sys_clock_hw_cycles_per_tick);
nrf_rtc_event_enable(SYS_CLOCK_RTC, RTC_EVTENSET_COMPARE0_Msk);
nrf_rtc_int_enable(SYS_CLOCK_RTC, RTC_INTENSET_COMPARE0_Msk);
/* Clear the event flag and possible pending interrupt */
RTC_CC_EVENT = 0;
NVIC_ClearPendingIRQ(NRF5_IRQ_RTC1_IRQn);
IRQ_CONNECT(NRF5_IRQ_RTC1_IRQn, 1, rtc1_nrf5_isr, 0, 0);
irq_enable(NRF5_IRQ_RTC1_IRQn);
nrf_rtc_task_trigger(SYS_CLOCK_RTC, NRF_RTC_TASK_CLEAR);
nrf_rtc_task_trigger(SYS_CLOCK_RTC, NRF_RTC_TASK_START);
return 0;
}
static int sys_clock_resume(struct device *dev)
{
ARG_UNUSED(dev);
*_REG_TIMER = reg_timer_save;
#ifndef CONFIG_MVIC
*_REG_TIMER_CFG = reg_timer_cfg_save;
#endif
/*
* It is difficult to accurately know the time spent in DS.
* We can use TSC or RTC but that will create a dependency
* on those components. Other issue is about what to do
* with pending timers. Following are some options :-
*
* 1) Expire all timers based on time spent found using some
* source like TSC
* 2) Expire all timers anyway
* 3) Expire only the timer at the top
* 4) Contine from where the timer left
*
* 1 and 2 require change to how timers are handled. 4 may not
* give a good user experience. After waiting for a long period
* in DS, the system would appear dead if it waits again.
*
* Current implementation uses option 3. The top most timer is
* expired. Following code will set the counter to a low number
* so it would immediately expire and generate timer interrupt
* which will process the top most timer. Note that timer IC
* cannot be set to 0. Setting it to 0 will stop the timer.
*/
initial_count_register_set(1);
loapic_timer_device_power_state = DEVICE_PM_ACTIVE_STATE;
return 0;
}
void uart_simple_isr(void *unused)
{
ARG_UNUSED(unused);
while (uart_irq_update(UART) && uart_irq_is_pending(UART)) {
int rx;
if (!uart_irq_rx_ready(UART)) {
continue;
}
rx = uart_fifo_read(UART, recv_buf + recv_off,
recv_buf_len - recv_off);
if (!rx) {
continue;
}
/* Call application callback with received data. Application
* may provide new buffer or alter data offset.
*/
recv_off += rx;
recv_buf = app_cb(recv_buf, &recv_off);
}
}
/*
* Do run-time initialization of pipe object subsystem.
*/
static int init_pipes_module(struct device *dev)
{
ARG_UNUSED(dev);
#if (CONFIG_NUM_PIPE_ASYNC_MSGS > 0)
/*
* Create pool of asynchronous pipe message descriptors.
*
* A dummy thread requires minimal initialization, since it never gets
* to execute. The _THREAD_DUMMY flag is sufficient to distinguish a
* dummy thread from a real one. The threads are *not* added to the
* kernel's list of known threads.
*
* Once initialized, the address of each descriptor is added to a stack
* that governs access to them.
*/
for (int i = 0; i < CONFIG_NUM_PIPE_ASYNC_MSGS; i++) {
async_msg[i].thread.thread_state = _THREAD_DUMMY;
async_msg[i].thread.swap_data = &async_msg[i].desc;
k_stack_push(&pipe_async_msgs, (u32_t)&async_msg[i]);
}
#endif /* CONFIG_NUM_PIPE_ASYNC_MSGS > 0 */
/* Complete initialization of statically defined mailboxes. */
#ifdef CONFIG_OBJECT_TRACING
struct k_pipe *pipe;
for (pipe = _k_pipe_list_start; pipe < _k_pipe_list_end; pipe++) {
SYS_TRACING_OBJ_INIT(k_pipe, pipe);
}
#endif /* CONFIG_OBJECT_TRACING */
return 0;
}
static void my_debug(void *ctx, int level,
const char *file, int line, const char *str)
{
const char *p, *basename;
int len;
ARG_UNUSED(ctx);
/* Extract basename from file */
for (p = basename = file; *p != '\0'; p++) {
if (*p == '/' || *p == '\\') {
basename = p + 1;
}
}
/* Avoid printing double newlines */
len = strlen(str);
if (str[len - 1] == '\n') {
((char *)str)[len - 1] = '\0';
}
NET_DBG("%s:%04d: |%d| %s", basename, line, level, str);
}
static UART_CONSOLE_OUT_DEBUG_HOOK_SIG(debug_hook_out_nop)
{
ARG_UNUSED(c);
return !UART_CONSOLE_DEBUG_HOOK_HANDLED;
}
void uart_console_isr(struct device *unused)
{
ARG_UNUSED(unused);
while (uart_irq_update(uart_console_dev) &&
uart_irq_is_pending(uart_console_dev)) {
static struct uart_console_input *cmd;
uint8_t byte;
int rx;
if (!uart_irq_rx_ready(uart_console_dev)) {
continue;
}
/* Character(s) have been received */
rx = read_uart(uart_console_dev, &byte, 1);
if (rx < 0) {
return;
}
if (uart_irq_input_hook(uart_console_dev, byte) != 0) {
/*
* The input hook indicates that no further processing
* should be done by this handler.
*/
return;
}
if (!cmd) {
cmd = nano_isr_fifo_get(avail_queue, TICKS_NONE);
if (!cmd)
return;
}
/* Handle ANSI escape mode */
if (atomic_test_bit(&esc_state, ESC_ANSI)) {
handle_ansi(byte);
continue;
}
/* Handle escape mode */
if (atomic_test_and_clear_bit(&esc_state, ESC_ESC)) {
switch (byte) {
case ANSI_ESC:
atomic_set_bit(&esc_state, ESC_ANSI);
atomic_set_bit(&esc_state, ESC_ANSI_FIRST);
break;
default:
break;
}
continue;
}
/* Handle special control characters */
if (!isprint(byte)) {
switch (byte) {
case DEL:
if (cur > 0) {
del_char(&cmd->line[--cur], end);
}
break;
case ESC:
atomic_set_bit(&esc_state, ESC_ESC);
break;
case '\r':
cmd->line[cur + end] = '\0';
uart_poll_out(uart_console_dev, '\r');
uart_poll_out(uart_console_dev, '\n');
cur = 0;
end = 0;
nano_isr_fifo_put(lines_queue, cmd);
cmd = NULL;
break;
case '\t':
if (completion_cb && !end) {
cur += completion_cb(cmd->line, cur);
}
break;
default:
break;
}
continue;
}
/* Ignore characters if there's no more buffer space */
if (cur + end < sizeof(cmd->line) - 1) {
insert_char(&cmd->line[cur++], byte, end);
}
}
}
void bt_uart_isr(void *unused)
{
static struct bt_buf *buf;
static int remaining;
ARG_UNUSED(unused);
while (uart_irq_update(UART) && uart_irq_is_pending(UART)) {
int read;
if (!uart_irq_rx_ready(UART)) {
if (uart_irq_tx_ready(UART)) {
BT_DBG("transmit ready\n");
} else {
BT_DBG("spurious interrupt\n");
}
continue;
}
/* Beginning of a new packet */
if (!remaining) {
uint8_t type;
/* Get packet type */
read = bt_uart_read(UART, &type, sizeof(type), 0);
if (read != sizeof(type)) {
BT_WARN("Unable to read H4 packet type\n");
continue;
}
switch (type) {
case H4_EVT:
buf = bt_uart_evt_recv(&remaining);
break;
case H4_ACL:
buf = bt_uart_acl_recv(&remaining);
break;
default:
BT_ERR("Unknown H4 type %u\n", type);
return;
}
if (buf && remaining > bt_buf_tailroom(buf)) {
BT_ERR("Not enough space in buffer\n");
goto failed;
}
BT_DBG("need to get %u bytes\n", remaining);
}
if (!buf) {
read = bt_uart_discard(UART, remaining);
BT_WARN("Discarded %d bytes\n", read);
remaining -= read;
continue;
}
read = bt_uart_read(UART, bt_buf_tail(buf), remaining, 0);
buf->len += read;
remaining -= read;
BT_DBG("received %d bytes\n", read);
if (!remaining) {
BT_DBG("full packet received\n");
/* Pass buffer to the stack */
bt_recv(buf);
buf = NULL;
}
}
return;
failed:
bt_buf_put(buf);
remaining = 0;
buf = NULL;
}
static int board_pinmux_init(struct device *dev)
{
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL);
struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL);
ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS
/* SERCOM0 on RX=PA11, TX=PA10 */
pinmux_pin_set(muxa, 11, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 10, PINMUX_FUNC_C);
#endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS
/* SERCOM5 on RX=PB23, TX=PB22 */
pinmux_pin_set(muxb, 23, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 22, PINMUX_FUNC_D);
#endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS
/* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */
pinmux_pin_set(muxa, 12, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 10, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 11, PINMUX_FUNC_D);
#endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured
#endif
#ifdef CONFIG_USB_DC_SAM0
/* USB DP on PA25, USB DM on PA24 */
pinmux_pin_set(muxa, 25, PINMUX_FUNC_G);
pinmux_pin_set(muxa, 24, PINMUX_FUNC_G);
#endif
return 0;
}
